Commit Graph

2484 Commits

Author SHA1 Message Date
Ahmed Bougacha
bed2308186 Add a way to define the bit range covered by a SubRegIndex.
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.

In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 17:08:36 +00:00
Bill Wendling
cc5a882c96 Don't reach into the middle of TargetMachine and cache one of its ivars.
Not only does this break encapsulation, it's gross.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182876 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29 20:37:19 +00:00
Preston Gurd
b704d23062 Convert sqrt functions into sqrt instructions when -ffast-math is in effect.
When -ffast-math is in effect (on Linux, at least), clang defines
__FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the
preprocessor to include <bits/math-finite.h>, which renames the sqrt functions.
For instance, "sqrt" is renamed as "__sqrt_finite". 

This patch adds the 3 new names in such a way that they will be treated
as equivalent to their respective original names.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-27 15:44:35 +00:00
Andrew Trick
ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-25 02:42:55 +00:00
Owen Anderson
f9c3ea31db Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 06:36:09 +00:00
Matt Arsenault
225ed7069c Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 00:21:46 +00:00
Jakob Stoklund Olesen
997fa623fc Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 18:03:08 +00:00
Rafael Espindola
4a971705bc Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 01:16:13 +00:00
Rafael Espindola
e449654815 Remove exception handling support from the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07 20:53:59 +00:00
Eric Christopher
3e39731e88 Move C++ code out of the C headers and into either C++ headers
or the C++ files themselves. This enables people to use
just a C compiler to interoperate with LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22 22:47:22 +00:00
Stephen Lin
94a720c73e Remove unused, undefined ArgFlagsTy::getArgFlagsString; add a comment about 'returned'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21 18:05:20 +00:00
Tim Northover
8b71994fde Remove unused ShouldFoldAtomicFences flag.
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 12:32:43 +00:00
Tim Northover
6265d5c91a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 12:32:17 +00:00
Stephen Lin
456ca048af Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 05:14:40 +00:00
Chad Rosier
88eb89b89f [asm parser] Add support for predicating MnemonicAlias based on the assembler
variant/dialect.  Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18 22:35:36 +00:00
Chad Rosier
05862c9788 Fix comment spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18 15:19:45 +00:00
Arnold Schwaighofer
cd3d60c450 TargetLowering: Fix getTypeConversion handling of extended vector types
The code in getTypeConversion attempts to promote the element vector type
before it trys to split or widen the vector.
After it failed finding a legal vector type by promoting it would continue using
the promoted vector element type. Thereby missing legal splitted vector types.
For example the type v32i32 that has a legal split of 4 x v3i32 on x86/sse2
would be transformed to: v32i256 and from there on successively split to:
v16i256, v8i256, v1i256 and then finally ends up as an i64 type.
By resetting the vector element type to the original vector element type that
existed before the promotion the code will attempt to split the vector type to
smaller vector widths of the same type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178999 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-07 20:22:56 +00:00
Hal Finkel
a36119beec Add a comment to TargetInstrInfo about FoldImmediate
This comment documents the current behavior of the ARM implementation of this
callback, and also the soon-to-be-committed PPC version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-06 19:30:20 +00:00
Bill Wendling
13bbe1f52e Use the target options specified on a function to reset the back-end.
During LTO, the target options on functions within the same Module may
change. This would necessitate resetting some of the back-end. Do this for X86,
because it's a Friday afternoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 21:52:40 +00:00
Jakob Stoklund Olesen
78dd7a580c Clean up some confusing language, and use more realistic examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 01:25:41 +00:00
Benjamin Kramer
74a4533a42 Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 17:14:24 +00:00
Jakob Stoklund Olesen
64110ffc9e Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {
    ...
  }

Which is now possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 22:51:13 +00:00
Reed Kotler
f8b0a08b6a Add a new method which enables one to change register classes.
See the Mips16ISetLowering.cpp patch to see a use of this.
For now now the extra code in Mips16ISetLowering.cpp is a nop but is
used for test purposes. Mips32 registers are setup and then removed and
then the Mips16 registers are setup. 

Normally you need to add register classes and then call
computeRegisterProperties.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 22:02:09 +00:00
Andrew Trick
1754aca83a MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:21:50 +00:00
Hal Finkel
3080d23fde Provide the register scavenger to processFunctionBeforeFrameFinalized
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.

This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 20:33:40 +00:00
Bill Wendling
4cb1f5f406 Reset some of the target options which affect code generation.
This doesn't reset all of the target options within the TargetOptions
object. This is because some of those are ABI-specific and must be determined if
it's okay to change those on the fly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13 22:26:59 +00:00
Meador Inge
cf70590c38 Add more functions to the TLI.
This patch adds many more functions to the target library information.
All of the functions being added were discovered while doing the migration
of the simplify-libcalls attribute annotation functionality to the
functionattrs pass.  As a part of that work the attribute annotation logic
will query TLI to determine if a function should be annotated or not.

Signed-off-by: Meador Inge <meadori@codesourcery.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 21:47:40 +00:00
Michael Liao
a6b20ced76 Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 18:40:30 +00:00
Eli Bendersky
700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 20:05:00 +00:00
Jim Grosbach
3450f800aa Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 21:13:59 +00:00
Benjamin Kramer
98fbe27ac8 Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 20:55:12 +00:00
Bill Wendling
789cb5df9c Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.
If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especially during LTO. We can do that by resetting the
subtarget's features depending upon the 'target-feature' attribute.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 22:31:27 +00:00
Tim Northover
ff9d058f28 Add deprecation of neverHasSideEffects to documentation comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 16:31:06 +00:00
Chad Rosier
108fb3202a [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 20:02:54 +00:00
Renato Golin
b3755e7fa2 Moving Cost Tables up to share with other targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24 23:01:00 +00:00
Chad Rosier
b09350d9a5 Initialize SSPBufferSize. PR14999. Patch by Vinson Lee.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23 19:32:37 +00:00
Benjamin Kramer
69e42dbd00 Split TargetLowering into a CodeGen and a SelectionDAG part.
This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still
a complete mess but as long as the edges consist of virtual call it doesn't
cause breakage. BasicTTI did static calls and thus broke some build
configurations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 20:05:37 +00:00
Jakub Staszak
674be02d52 Fix include guards so they exactly match file names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 00:45:19 +00:00
David Tweed
73b984530f For some LLVM-as-library uses it is convenient to create a
subclass of TargetMachine which "forwards" all operations to an
existing internal TargetMachine member variable. In the usage context the
specific-machine class derived from TargetMachine is not visible,
only a reference to the generic base class TargetMachine. Although
getSubtargetImpl() is public in specific-machine classes derived from
TargetMachine, the TargetMachine class unfortunately has
getSubtargetImpl() protected (and accessing non-const members makes
abusing getSubtarget() unsuitable). Making it public in the base class
allows this forwarding pattern.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171976 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 16:21:47 +00:00
Tim Northover
2c8cf4b404 Refactor to expose RTLIB calls to targets.
fp128 is almost but not quite completely illegal as a type on AArch64. As a
result it needs to have a register class (for argument passing mainly), but all
operations need to be lowered to runtime calls. Currently there's no way for
targets to do this (without duplicating code), as the relevant functions are
hidden in SelectionDAG. This patch changes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171971 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 13:18:15 +00:00
Andrew Trick
47579cf390 MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 03:36:49 +00:00
Chandler Carruth
56d433dffe Sink AddrMode back into TargetLowering, removing one of the most
peculiar headers under include/llvm.

This struct still doesn't make a lot of sense, but it makes more sense
down in TargetLowering than it did before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 15:14:13 +00:00
Chandler Carruth
aeef83c6af Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.

The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.

The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.

The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.

The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.

The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.

The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.

The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.

Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.

Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.

Commits to update DragonEgg and Clang will be made presently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07 01:37:14 +00:00
Chandler Carruth
64e407be0d Refactor the ScalarTargetTransformInfo API for querying about the
legality of an address mode to not use a struct of four values and
instead to accept them as parameters. I'd love to have named parameters
here as most callers only care about one or two of these, but the
defaults aren't terribly scary to write out.

That said, there is no real impact of this as the passes aren't yet
using STTI for this and are still relying upon TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171595 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-05 03:36:17 +00:00
Nadav Rotem
e503319874 LoopVectorizer:
1. Add code to estimate register pressure.
2. Add code to select the unroll factor based on register pressure.
3. Add bits to TargetTransformInfo to provide the number of registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-04 17:48:25 +00:00
Hal Finkel
82860f63e1 Add a subtype parameter to VTTI::getShuffleCost
In order to cost subvector insertion and extraction, we need to know
the type of the subvector being extracted.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171453 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-03 02:34:09 +00:00
Chandler Carruth
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Bill Wendling
8b62abdd7b Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 13:01:51 +00:00
Nadav Rotem
3190be9c9a DAGCombinerInformation: add a getter that exposes the dagcombine level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 08:44:35 +00:00
Nadav Rotem
444b4bf5c8 Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 06:47:41 +00:00