llvm-6502/lib/CodeGen
Andrew Lenharth c1c7bd610a Better names as per Evan's request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47435 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-21 16:11:38 +00:00
..
SelectionDAG Better names as per Evan's request 2008-02-21 16:11:38 +00:00
AsmPrinter.cpp Update gcc 4.3 warnings fix patch with recent head changes 2008-02-20 11:10:28 +00:00
BranchFolding.cpp PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in order to save a single instruction since a branch will be inserted for each BB. 2008-02-19 02:09:37 +00:00
Collector.cpp Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. 2008-01-31 09:59:15 +00:00
CollectorMetadata.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
Collectors.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
DwarfWriter.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
ELFWriter.cpp Enable exception handling int JIT 2008-02-13 18:39:37 +00:00
ELFWriter.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
IfConversion.cpp Update gcc 4.3 warnings fix patch with recent head changes 2008-02-20 11:10:28 +00:00
IntrinsicLowering.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
LiveInterval.cpp Update gcc 4.3 warnings fix patch with recent head changes 2008-02-20 11:10:28 +00:00
LiveIntervalAnalysis.cpp Clean up some spilling code using MachineRegisterInfo. 2008-02-21 00:34:19 +00:00
LiveVariables.cpp Remove one of the fixmes that I put in there. From Evan: 2008-02-20 20:56:45 +00:00
LLVMTargetMachine.cpp Enable exception handling int JIT 2008-02-13 18:39:37 +00:00
LowerSubregs.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
MachineBasicBlock.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
MachineDominators.cpp Fix build issue on certain compilers. 2008-01-05 20:15:42 +00:00
MachineFunction.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
MachineInstr.cpp Support a new type of MachineOperand, MO_FPImmediate, used for holding 2008-02-14 07:39:30 +00:00
MachineLICM.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
MachineLoopInfo.cpp make this build with newer gcc's 2008-01-05 23:29:51 +00:00
MachineModuleInfo.cpp SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. 2008-02-02 04:07:54 +00:00
MachinePassRegistry.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
MachineRegisterInfo.cpp Added debugging routine dumpUses. 2008-02-13 02:45:38 +00:00
MachineSink.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
MachOWriter.cpp Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings. 2008-02-20 11:08:44 +00:00
MachOWriter.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
Makefile remove attribution from lib Makefiles. 2007-12-29 20:09:26 +00:00
OcamlCollector.cpp Pruning includes. 2008-01-07 13:30:38 +00:00
Passes.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
PHIElimination.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
PhysRegTracker.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
PostRASchedulerList.cpp don't create the post-ra scheduler unless it is enabled. 2008-01-14 19:00:06 +00:00
PrologEpilogInserter.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
PseudoSourceValue.cpp From Chris' review: fix 80 column violations 2008-02-11 18:57:43 +00:00
README.txt add anote 2008-02-10 01:01:35 +00:00
RegAllocBigBlock.cpp Update gcc 4.3 warnings fix patch with recent head changes 2008-02-20 11:10:28 +00:00
RegAllocLinearScan.cpp Fix newly-introduced 4.3 warnings 2008-02-20 12:07:57 +00:00
RegAllocLocal.cpp Fix newly-introduced 4.3 warnings 2008-02-20 12:07:57 +00:00
RegAllocSimple.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
RegisterCoalescer.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
RegisterScavenging.cpp Fix typos. 2008-02-16 01:09:25 +00:00
ShadowStackCollector.cpp Don't dump the function! 2008-01-24 19:28:11 +00:00
SimpleRegisterCoalescing.cpp - Remove the previous check which broke coalescer-commute3.ll 2008-02-18 18:56:31 +00:00
SimpleRegisterCoalescing.h Refactor some code; check if commuteInstruction is able to commute the instruction. 2008-02-16 02:32:17 +00:00
StrongPHIElimination.cpp Fix an iterator invalidation issue. 2008-01-22 23:58:54 +00:00
TargetInstrInfoImpl.cpp Added CommuteChangesDestination(). This returns true if commuting the specified 2008-02-15 18:21:33 +00:00
TwoAddressInstructionPass.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
UnreachableBlockElim.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
VirtRegMap.cpp Update gcc 4.3 warnings fix patch with recent head changes 2008-02-20 11:10:28 +00:00
VirtRegMap.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
	ldr r3, [sp, #+4]
	add r3, r3, #3
	ldr r2, [sp, #+8]
	add r2, r2, #2
	ldr r1, [sp, #+4]  <==
	add r1, r1, #1
	ldr r0, [sp, #+4]
	add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//