llvm-6502/lib/CodeGen/SelectionDAG
Chris Lattner c2c28fc24c Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
for tied register constraints.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37601 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-15 19:11:01 +00:00
..
CallingConvLower.cpp
DAGCombiner.cpp Rename MVT::getVectorBaseType to MVT::getVectorElementType. 2007-06-14 22:58:02 +00:00
LegalizeDAG.cpp Rename MVT::getVectorBaseType to MVT::getVectorElementType. 2007-06-14 22:58:02 +00:00
Makefile
ScheduleDAG.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSimple.cpp
SelectionDAG.cpp Rename MVT::getVectorBaseType to MVT::getVectorElementType. 2007-06-14 22:58:02 +00:00
SelectionDAGISel.cpp Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info 2007-06-15 19:11:01 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp