llvm-6502/lib/CodeGen/SelectionDAG
Hal Finkel c404e8208c Optionally enable more-aggressive FMA formation in DAGCombine
The heuristic used by DAGCombine to form FMAs checks that the FMUL has only one
use, but this is overly-conservative on some systems. Specifically, if the FMA
and the FADD have the same latency (and the FMA does not compete for resources
with the FMUL any more than the FADD does), there is no need for the
restriction, and furthermore, forming the FMA leaving the FMUL can still allow
for higher overall throughput and decreased critical-path length.

Here we add a new TLI callback, enableAggressiveFMAFusion, false by default, to
elide the hasOneUse check. This is enabled for PowerPC by default, as most
PowerPC systems will benefit.

Patch by Olivier Sallenave, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218120 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-19 11:42:56 +00:00
..
CMakeLists.txt
DAGCombiner.cpp Optionally enable more-aggressive FMA formation in DAGCombine 2014-09-19 11:42:56 +00:00
FastISel.cpp [FastISel] Move optimizeCmpPredicate to FastISel base class. NFC. 2014-09-15 20:47:13 +00:00
FunctionLoweringInfo.cpp Optimize sext/zext insertion algorithm in back-end. 2014-09-19 05:30:35 +00:00
InstrEmitter.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
InstrEmitter.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
LegalizeDAG.cpp Replace dead links to "Hacker's Delight" with general references. NFC. 2014-09-15 19:47:44 +00:00
LegalizeFloatTypes.cpp ARM: fix @llvm.convert.from.fp16 on softfloat targets. 2014-07-29 09:56:38 +00:00
LegalizeIntegerTypes.cpp Optimize sext/zext insertion algorithm in back-end. 2014-09-19 05:30:35 +00:00
LegalizeTypes.cpp Make it possible for ints/floats to return different values from getBooleanContents() 2014-07-10 10:18:12 +00:00
LegalizeTypes.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
LegalizeTypesGeneric.cpp AA metadata refactoring (introduce AAMDNodes) 2014-07-24 12:16:19 +00:00
LegalizeVectorOps.cpp Teach the AArch64 backend about v4f16 and v8f16 2014-08-27 16:16:04 +00:00
LegalizeVectorTypes.cpp Allow targets to custom legalize vector insertion and extraction. 2014-09-12 22:16:11 +00:00
LLVMBuild.txt
Makefile
ResourcePriorityQueue.cpp Change MCSchedModel to be a struct of statically initialized data. 2014-09-02 17:43:54 +00:00
ScheduleDAGFast.cpp [Modules] Remove potential ODR violations by sinking the DEBUG_TYPE 2014-04-22 02:02:50 +00:00
ScheduleDAGRRList.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
ScheduleDAGSDNodes.cpp Make this SmallVector size a power of two as suggested by Chandler 2014-08-11 13:47:57 +00:00
ScheduleDAGSDNodes.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
ScheduleDAGVLIW.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
SDNodeDbgValue.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SelectionDAG.cpp Do not assume the value passed to memset is an i32. 2014-08-29 08:23:53 +00:00
SelectionDAGBuilder.cpp Optimize sext/zext insertion algorithm in back-end. 2014-09-19 05:30:35 +00:00
SelectionDAGBuilder.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SelectionDAGDumper.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SelectionDAGISel.cpp [FastISel] Rename public visible FastISel functions. NFC. 2014-09-03 20:56:52 +00:00
SelectionDAGPrinter.cpp Revert "Introduce a string_ostream string builder facilty" 2014-06-26 22:52:05 +00:00
TargetLowering.cpp Replace repeated null checks with an assert. NFC. 2014-09-15 21:52:51 +00:00
TargetSelectionDAGInfo.cpp Have TargetSelectionDAGInfo take a DataLayout initializer rather than 2014-06-06 19:04:48 +00:00