Commit Graph

6589 Commits

Author SHA1 Message Date
Hal Finkel
c404e8208c Optionally enable more-aggressive FMA formation in DAGCombine
The heuristic used by DAGCombine to form FMAs checks that the FMUL has only one
use, but this is overly-conservative on some systems. Specifically, if the FMA
and the FADD have the same latency (and the FMA does not compete for resources
with the FMUL any more than the FADD does), there is no need for the
restriction, and furthermore, forming the FMA leaving the FMUL can still allow
for higher overall throughput and decreased critical-path length.

Here we add a new TLI callback, enableAggressiveFMAFusion, false by default, to
elide the hasOneUse check. This is enabled for PowerPC by default, as most
PowerPC systems will benefit.

Patch by Olivier Sallenave, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218120 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-19 11:42:56 +00:00
Jiangning Liu
61519cd699 Optimize sext/zext insertion algorithm in back-end.
With this optimization, we will not always insert zext for values crossing
basic blocks, but insert sext if the users of a value crossing basic block
has preference of sign predicate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218101 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-19 05:30:35 +00:00
Sanjay Patel
ec6117cf1d Replace repeated null checks with an assert. NFC.
Without a vector to hold the created ops, these 
functions don't have any use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217831 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 21:52:51 +00:00
Juergen Ributzka
1ee1e8bdc2 [FastISel] Move optimizeCmpPredicate to FastISel base class. NFC.
Make the optimizeCmpPredicate function available to all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 20:47:13 +00:00
Sanjay Patel
6c7ec4aae9 Replace dead links to "Hacker's Delight" with general references. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217814 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 19:47:44 +00:00
Owen Anderson
00edf1f086 Allow targets to custom legalize vector insertion and extraction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 22:16:11 +00:00
Benjamin Kramer
66feb63c3c Legalizer: Use the scalar bit width when promoting bit counting instrs on
vectors.

e.g. when promoting ctlz from <2 x i32> to <2 x i64> we have to fixup
the result by 32 bits, not 64. PR20917.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 12:50:27 +00:00
Matt Arsenault
31b1bdbd95 Add DAG combine for shl + add of constants.
Do
 (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)

This is already done for multiplies, but since multiplies
by powers of two are turned into shifts, we also need
to handle it here.

This might want checks for isLegalAddImmediate to avoid
transforming an add of a legal immediate with one that isn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-11 17:34:19 +00:00
Sanjay Patel
04bb0e721f Combine fmul vector FP constants when unsafe math is allowed.
This is an extension of the change made with r215820:
http://llvm.org/viewvc/llvm-project?view=revision&revision=215820

That patch allowed combining of splatted vector FP constants that are multiplied.

This patch allows combining non-uniform vector FP constants too by relaxing the
check on the type of vector. Also, canonicalize a vector fmul in the
same way that we already do for scalars - if only one operand of the fmul is a
constant, make it operand 1. Otherwise, we miss potential folds.

This fold is also done by -instcombine, but it's possible that extra
fmuls may have been generated during lowering.

Differential Revision: http://reviews.llvm.org/D5254



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-11 15:45:27 +00:00
David Xu
65aac0f8e3 Build correct vector filled with undef nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217570 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-11 05:10:28 +00:00
Hans Wennborg
4cd53531fd Fast-ISel: Remove dead code after falling back from selecting call instructions (PR20863)
Previously, fast-isel would not clean up after failing to select a call
instruction, because it would have called flushLocalValueMap() which moves
the insertion point, making SavedInsertPt in selectInstruction() invalid.

Fixing this by making SavedInsertPt a member variable, and having
flushLocalValueMap() update it.

This removes some redundant code at -O0, and more importantly fixes PR20863.

Differential Revision: http://reviews.llvm.org/D5249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217401 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-08 20:24:10 +00:00
Sanjay Patel
50a5cda135 Group unsafe fmul math folds together for easier reading. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217399 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-08 20:16:42 +00:00
Sanjay Patel
16ee570cc3 Fix the FIXME that was just added in r217390 - remove a bunch of redundant fold permutations.
The testcases for these folds already exist in test/CodeGen/X86/fp-fast.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217393 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-08 18:22:51 +00:00
Sanjay Patel
f6ab875af0 group unsafe math folds together for easier reading
Also added a FIXME regarding redundant folds for non-canonicalized constants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217390 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-08 17:32:19 +00:00
Sanjay Patel
52af82df95 Allow vector fsub ops with constants to get the same optimizations as scalars.
This problem is bigger than just fsub, but this is the minimum fix to solve
fneg for PR20556 ( http://llvm.org/bugs/show_bug.cgi?id=20556 ), and we solve
zero subtraction with the same change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-05 22:26:22 +00:00
Sanjay Patel
2d1c2853e1 clean up; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217278 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-05 20:55:46 +00:00
Juergen Ributzka
ecadea992a [FastISel][tblgen] Rename tblgen generated FastISel functions. NFC.
This is the final round of renaming. This changes tblgen to emit lower-case
function names for FastEmitInst_* and FastEmit_*, and updates all its uses
in the source code.

Reviewed by Eric

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217075 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 20:56:59 +00:00
Juergen Ributzka
6042034603 [FastISel] Rename public visible FastISel functions. NFC.
This commit renames the following public FastISel functions:
LowerArguments -> lowerArguments
SelectInstruction -> selectInstruction
TargetSelectInstruction -> fastSelectInstruction
FastLowerArguments -> fastLowerArguments
FastLowerCall -> fastLowerCall
FastLowerIntrinsicCall -> fastLowerIntrinsicCall
FastEmitZExtFromI1 -> fastEmitZExtFromI1
FastEmitBranch -> fastEmitBranch
UpdateValueMap -> updateValueMap
TargetMaterializeConstant -> fastMaterializeConstant
TargetMaterializeAlloca -> fastMaterializeAlloca
TargetMaterializeFloatZero -> fastMaterializeFloatZero
LowerCallTo -> lowerCallTo

Reviewed by Eric

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217074 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 20:56:52 +00:00
Eric Christopher
5b7ae59f6d Remove resetSubtargetFeatures as it is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217071 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 20:36:31 +00:00
Juergen Ributzka
39af4e655a [FastISel] Some long overdue spring cleaning of FastISel.
Things got a little bit messy over the years and it is time for a little bit
spring cleaning.

This first commit is focused on the FastISel base class itself. It doxyfies all
comments, C++11fies the code where it makes sense, renames internal methods to
adhere to the coding standard, and clang-formats the files.

Reviewed by Eric

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217060 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 18:46:45 +00:00
Eric Christopher
d5dd8ce2a5 Reinstate "Nuke the old JIT."
Approved by Jim Grosbach, Lang Hames, Rafael Espindola.

This reinstates commits r215111, 215115, 215116, 215117, 215136.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216982 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 22:28:02 +00:00
Juergen Ributzka
37753c5f9d [FastISel] Provide the option to skip target-independent instruction selection. NFC.
This allows the target to disable target-independent instruction selection and
jump directly into the target-dependent instruction selection code.

This can be beneficial for targets, such as AArch64, which could emit much
better code, but never got a chance to do so, because the target-independent
instruction selector was able to find an instruction sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216947 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 21:07:44 +00:00
Matt Arsenault
f7a3c7e705 Fix interference caused by fmul 2, x -> fadd x, x
If an fmul was introduced by lowering, it wouldn't be folded
into a multiply by a constant since the earlier combine would
have replaced the fmul with the fadd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 19:02:53 +00:00
Reid Kleckner
f93099eb1c CodeGen: Handle va_start in the entry block
Also fix a small copy-paste bug in X86ISelLowering where Chain should
have been used in place of DAG.getEntryToken().

Fixes PR20828.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216929 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:42:44 +00:00
Matt Arsenault
1c7650f67c Fix comment and unnecessary check for FP build_vectors.
This was copy-paste from the integer version, but
FP build_vectors don't truncate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216928 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 18:33:51 +00:00
Pete Cooper
6de6c6aae4 Change MCSchedModel to be a struct of statically initialized data.
This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour

Reviewed by Andy Trick and Chandler C

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216919 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:43:54 +00:00
Hal Finkel
2633f795c6 Enable splitting indexing from loads with TargetConstants
When I recommitted r208640 (in r216898) I added an exclusion for TargetConstant
offsets, as there is no guarantee that a backend can handle them on generic
ADDs (even if it generates them during address-mode matching) -- and,
specifically, applying this transformation directly with TargetConstants caused
a self-hosting failure on PPC64. Ignoring all TargetConstants, however, is less
than ideal. Instead, for non-opaque constants, we can convert them into regular
constants for use with the generated ADD (or SUB).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 16:05:23 +00:00
Hal Finkel
3da41a28a1 Revert "Revert '[DAGCombiner] Split up an indexed load if only the base pointer value is live'"
I reverted r208640 in r209747 because r208640 broke self-hosting on PPC64. The
underlying cause of the failure is that pre-inc loads with increments
represented by ISD::TargetConstants were being transformed into ISD:::ADDs with
ISD::TargetConstant operands. PPC doesn't have a pattern for those, and so they
were selected as invalid r+r adds.

This recommits r208640, rebased and with an exclusion for ISD::TargetConstant
increments. This behavior seems correct, although in the future we might want
to ask the target to split out the indexing that uses ISD::TargetConstants.

Unfortunately, I don't yet have small test case where the relevant invalid
'add' instruction is not itself dead (and thus eliminated by
DeadMachineInstructionElim -- sometimes bugpoint is too good at removing things)

Original commit message (by Adam Nemet):

Right now the load may not get DCE'd because of the side-effect of updating
the base pointer.

This can happen if we lower a read-modify-write of an illegal larger type
(e.g. i48) such that the modification only affects one of the subparts (the
lower i32 part but not the higher i16 part).  See the testcase.

In order to spot the dead load we need to revisit it when SimplifyDemandedBits
decided that the value of the load is masked off.  This is the
CommitTargetLoweringOpt piece.

I checked compile time with ARM64 by sending SPEC bitcode files through llc.
No measurable change.

Fixes <rdar://problem/16031651>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 06:24:04 +00:00
Reid Kleckner
039f6c6ded Add a const and munge some comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-29 21:42:21 +00:00
Reid Kleckner
9436574d1b musttail: Forward regparms of variadic functions on x86_64
Summary:
If a variadic function body contains a musttail call, then we copy all
of the remaining register parameters into virtual registers in the
function prologue. We track the virtual registers through the function
body, and add them as additional registers to pass to the call. Because
this is all done in virtual registers, the register allocator usually
gives us good code. If the function does a call, however, it will have
to spill and reload all argument registers (ew).

Forwarding regparms on x86_32 is not implemented because most compilers
don't support varargs in 32-bit with regparms.

Reviewers: majnemer

Subscribers: aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D5060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216780 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-29 21:42:08 +00:00
Job Noorman
d2323fc295 Do not assume the value passed to memset is an i32.
The code in SelectionDAG::getMemset for some reason assumes the value passed to
memset is an i32. This breaks the generated code for targets that only have
registers smaller than 32 bits because the value might get split into multiple
registers by the calling convention. See the test for the MSP430 target included
in the patch for an example.

This patch ensures that nothing is assumed about the type of the value. Instead,
the type is taken from the selected overload of the llvm.memset intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216716 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-29 08:23:53 +00:00
Sanjay Patel
179b5ee8a8 Move FNEG next to FABS and make them more similar, so it's easier that they can be refactored. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216688 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-28 21:51:37 +00:00
Owen Anderson
538b1cbdf5 Do not introduce new shuffle patterns after operation legalization if SHUFFLE_VECTOR
was marked custom.  The target independent DAG combine has no way to know if
the shuffles it is introducing are ones that the target could support or not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216678 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-28 17:49:58 +00:00
Sanjay Patel
98491c0ff9 Janitorial services: "Don’t duplicate function or class name at the beginning of the comment."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216674 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-28 16:29:51 +00:00
Sanjay Patel
e43c262106 Remove local TLI vars that are just duplicates of the class var. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216673 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-28 16:01:50 +00:00
Sanjay Patel
a63b6e2840 Use local vars to improve readability. No functional change.
Completes what was started in r216611 and r216623. 
Used const refs instead of pointers; not sure if one is preferable to the other.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216672 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-28 15:53:16 +00:00
Juergen Ributzka
4a76317ebb [FastISel] Undo phi node updates when falling-back to SelectionDAG.
The included test case would fail, because the MI PHI node would have two
operands from the same predecessor.

This problem occurs when a switch instruction couldn't be selected. This happens
always, because there is no default switch support for FastISel to begin with.

The problem was that FastISel would first add the operand to the PHI nodes and
then fall-back to SelectionDAG, which would then in turn add the same operands
to the PHI nodes again.

This fix removes these duplicate PHI node operands by reseting the
PHINodesToUpdate to its original state before FastISel tried to select the
instruction.

This fixes <rdar://problem/18155224>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216640 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-28 02:06:55 +00:00
Juergen Ributzka
d24494d672 [FastISel]
Currently instructions are folded very aggressively for AArch64 into the memory
operation, which can lead to the use of killed operands:
  %vreg1<def> = ADDXri %vreg0<kill>, 2
  %vreg2<def> = LDRBBui %vreg0, 2
  ... = ... %vreg1 ...

This usually happens when the result is also used by another non-memory
instruction in the same basic block, or any instruction in another basic block.

This fix teaches hasTrivialKill to not only check the LLVM IR that the value has
a single use, but also to check if the register that represents that value has
already been used. This can happen when the instruction with the use was folded
into another instruction (in this particular case a load instruction).

This fixes rdar://problem/18142857.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-28 00:09:46 +00:00
Sanjay Patel
a160df5b42 Use local variable in visitFADD. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216623 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 21:42:42 +00:00
Sanjay Patel
305938e272 Group unsafe-math optimizations for fsub into one block. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 20:57:52 +00:00
Juergen Ributzka
fc68dad43c [FastISel] Fix a potential bug in FastEmitInst_ri
FastEmitInst_ri was constraining the first operand without checking if it is
a virtual register. Use constrainOperandRegClass as all the other
FastEmitInst_* functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 20:47:33 +00:00
Sanjay Patel
5b92f447ab Use local variable to improve readability.
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 20:40:31 +00:00
Oliver Stannard
5e487f8dc7 Teach the AArch64 backend about v4f16 and v8f16
This teaches the AArch64 backend to deal with the operations required
to deal with the operations on v4f16 and v8f16 which are exposed by
NEON intrinsics, plus the add, sub, mul and div operations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216555 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 16:16:04 +00:00
Chandler Carruth
963a5e6c61 [SDAG] Re-instate r215611 with a fix to a pesky X86 DAG combine.
This combine is essentially combining target-specific nodes back into target
independent nodes that it "knows" will be combined yet again by a target
independent DAG combine into a different set of target-independent nodes that
are legal (not custom though!) and thus "ok". This seems... deeply flawed. The
crux of the problem is that we don't combine un-legalized shuffles that are
introduced by legalizing other operations, and thus we don't see a very
profitable combine opportunity. So the backend just forces the input to that
combine to re-appear.

However, for this to work, the conditions detected to re-form the unlegalized
nodes must be *exactly* right. Previously, failing this would have caused poor
code (if you're lucky) or a crasher when we failed to select instructions.
After r215611 we would fall back into the legalizer. In some cases, this just
"fixed" the crasher by produces bad code. But in the test case added it caused
the legalizer and the dag combiner to iterate forever.

The fix is to make the alignment checking in the x86 side of things match the
alignment checking in the generic DAG combine exactly. This isn't really a
satisfying or principled fix, but it at least make the code work as intended.
It also highlights that it would be nice to detect the availability of under
aligned loads for a given type rather than bailing on this optimization. I've
left a FIXME to document this.

Original commit message for r215611 which covers the rest of the chang:
  [SDAG] Fix a case where we would iteratively legalize a node during
  combining by replacing it with something else but not re-process the
  node afterward to remove it.

  In a truly remarkable stroke of bad luck, this would (in the test case
  attached) end up getting some other node combined into it without ever
  getting re-processed. By adding it back on to the worklist, in addition
  to deleting the dead nodes more quickly we also ensure that if it
  *stops* being dead for any reason it makes it back through the
  legalizer. Without this, the test case will end up failing during
  instruction selection due to an and node with a type we don't have an
  instruction pattern for.

It took many million runs of the shuffle fuzz tester to find this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216537 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 11:22:16 +00:00
Craig Topper
3512034554 Simplify creation of a bunch of ArrayRefs by using None, makeArrayRef or just letting them be implicitly created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216525 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-27 05:25:25 +00:00
Craig Topper
273fd11da9 Use range based for loops to avoid needing to re-mention SmallPtrSet size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-24 23:23:06 +00:00
Nick Lewycky
f591b9c33e Revert r215611 because it caused the infinite loop in bug 20736. There is a reduced testcase in that bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216307 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-23 00:45:03 +00:00
Reid Kleckner
d89c0abc07 ARM / x86_64 varargs: Don't save regparms in prologue without va_start
There's no need to do this if the user doesn't call va_start. In the
future, we're going to have thunks that forward these register
parameters with musttail calls, and they won't need these spills for
handling va_start.

Most of the test suite changes are adding va_start calls to existing
tests to keep things working.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216294 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-22 21:59:26 +00:00
Sanjay Patel
d1a09c47d2 name change: isPow2DivCheap -> isPow2SDivCheap
isPow2DivCheap

That name doesn't specify signed or unsigned.

Lazy as I am, I eventually read the function and variable comments. It turns out that this is strictly about signed div. But I discovered that the comments are wrong:

   srl/add/sra

is not the general sequence for signed integer division by power-of-2. We need one more 'sra':

   sra/srl/add/sra

That's the sequence produced in DAGCombiner. The first 'sra' may be removed when dividing by exactly '2', but that's a special case.

This patch corrects the comments, changes the name of the flag bit, and changes the name of the accessor methods.

No functional change intended.

Differential Revision: http://reviews.llvm.org/D5010


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216237 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 22:31:48 +00:00
Benjamin Kramer
daada81e5c DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments.
PR20677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 13:28:02 +00:00