Matt Arsenault d796cf2e01 Enable (sext x) == C --> x == (trunc C) combine ...

Extend the existing code which handles this for zext. This makes this
more useful for targets with ZeroOrNegativeOne BooleanContent and
obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne)
since the constant will now be shrunk to i1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224691 91177308-0d34-0410-b5e6-96231b3b80d8

2014-12-21 16:48:42 +00:00

..

AsmParser

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InstPrinter

R600/SI: Fix f64 inline immediates

2014-12-17 21:04:08 +00:00

MCTargetDesc

R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand

2014-12-19 22:15:30 +00:00

TargetInfo

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AMDGPU.h

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AMDGPU.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUAlwaysInlinePass.cpp

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AMDGPUAsmPrinter.cpp

Silencing a 32-bit implicit conversion warning in MSVC; NFC.

2014-12-03 14:39:58 +00:00

AMDGPUAsmPrinter.h

R600/SI: Emit amd_kernel_code_t header for AMDGPU environment

2014-12-02 22:00:07 +00:00

AMDGPUCallingConv.td

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

…

AMDGPUInstrInfo.cpp

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUInstrInfo.h

…

AMDGPUInstrInfo.td

R600/SI: fmin/fmax_legacy are not associative

2014-12-12 02:30:33 +00:00

AMDGPUInstructions.td

R600/SI: Make more unordered comparisons legal

2014-12-11 22:15:39 +00:00

AMDGPUIntrinsicInfo.cpp

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AMDGPUIntrinsicInfo.h

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AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime

2014-12-02 17:05:41 +00:00

AMDGPUISelLowering.cpp

R600: Remove outdated comment

2014-12-19 23:29:13 +00:00

AMDGPUISelLowering.h

R600: Fix min/max matching problems with unordered compares

2014-12-12 02:30:37 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

…

AMDGPUMCInstLower.cpp

R600/SI: Fix f64 inline immediates

2014-12-17 21:04:08 +00:00

AMDGPUMCInstLower.h

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUPromoteAlloca.cpp

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AMDGPURegisterInfo.cpp

R600/SI: Enable inline assembly

2014-12-03 04:08:00 +00:00

AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

…

AMDGPUSubtarget.cpp

R600/SI: Emit amd_kernel_code_t header for AMDGPU environment

2014-12-02 22:00:07 +00:00

AMDGPUSubtarget.h

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

AMDGPUTargetMachine.cpp

[CodeGen] Add print and verify pass after each MachineFunctionPass by default

2014-12-11 21:26:47 +00:00

AMDGPUTargetMachine.h

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AMDGPUTargetTransformInfo.cpp

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AMDILCFGStructurizer.cpp

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AMDKernelCodeT.h

R600/SI: Emit amd_kernel_code_t header for AMDGPU environment

2014-12-02 22:00:07 +00:00

CaymanInstructions.td

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CIInstructions.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

CMakeLists.txt

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EvergreenInstructions.td

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LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

R600ClauseMergePass.cpp

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R600ControlFlowFinalizer.cpp

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R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600InstrFormats.td

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R600InstrInfo.cpp

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R600InstrInfo.h

…

R600Instructions.td

R600/SI: Use unordered not equal instructions

2014-12-11 22:15:35 +00:00

R600Intrinsics.td

…

R600ISelLowering.cpp

R600: Fix min/max matching problems with unordered compares

2014-12-12 02:30:37 +00:00

R600ISelLowering.h

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R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

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R600Packetizer.cpp

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R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

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R700Instructions.td

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SIAnnotateControlFlow.cpp

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SIDefines.h

R600/SI: Move more information into SIProgramInfo struct

2014-12-02 21:28:53 +00:00

SIFixSGPRCopies.cpp

R600/SI: Fix SIFixSGPRCopies for copies to physical registers

2014-12-03 05:22:39 +00:00

SIFixSGPRLiveRanges.cpp

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SIFoldOperands.cpp

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SIInsertWaits.cpp

R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOP

2014-12-07 17:17:43 +00:00

SIInstrFormats.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

SIInstrInfo.cpp

R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructions

2014-12-19 22:15:37 +00:00

SIInstrInfo.h

R600/SI: Set 20-bit immediate byte offset for SMRD on VI

2014-12-07 17:17:38 +00:00

SIInstrInfo.td

R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand

2014-12-19 22:15:30 +00:00

SIInstructions.td

R600/SI: Fix f64 inline immediates

2014-12-17 21:04:08 +00:00

SIIntrinsics.td

…

SIISelLowering.cpp

Enable (sext x) == C --> x == (trunc C) combine

2014-12-21 16:48:42 +00:00

SIISelLowering.h

…

SILoadStoreOptimizer.cpp

R600/SI: Fix live range error hidden by SIFoldOperands

2014-12-03 05:22:29 +00:00

SILowerControlFlow.cpp

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SILowerI1Copies.cpp

R600/SI: Remove i1 pseudo VALU ops

2014-12-03 05:22:35 +00:00

SIMachineFunctionInfo.cpp

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SIMachineFunctionInfo.h

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SIRegisterInfo.cpp

R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand

2014-12-19 22:15:30 +00:00

SIRegisterInfo.h

…

SIRegisterInfo.td

R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand

2014-12-19 22:15:30 +00:00

SISchedule.td

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SIShrinkInstructions.cpp

R600/SI: Move continue after checking s_mov_b32.

2014-12-08 19:55:43 +00:00

SITypeRewriter.cpp

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VIInstrFormats.td

R600/SI: Add VI instructions

2014-12-07 12:18:57 +00:00

VIInstructions.td

R600/SI: Set 20-bit immediate byte offset for SMRD on VI

2014-12-07 17:17:38 +00:00