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c9c8b2a804
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8 |
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|---|---|---|
| .. | ||
| useful-harnesses | ||
| 2009-01-01-BrCond.ll | ||
| and_ops.ll | ||
| call_indirect.ll | ||
| call.ll | ||
| ctpop.ll | ||
| dg.exp | ||
| dp_farith.ll | ||
| eqv.ll | ||
| extract_elt.ll | ||
| fcmp32.ll | ||
| fcmp64.ll | ||
| fdiv.ll | ||
| fneg-fabs.ll | ||
| i8ops.ll | ||
| i64ops.ll | ||
| icmp8.ll | ||
| icmp16.ll | ||
| icmp32.ll | ||
| icmp64.ll | ||
| immed16.ll | ||
| immed32.ll | ||
| immed64.ll | ||
| int2fp.ll | ||
| intrinsics_branch.ll | ||
| intrinsics_float.ll | ||
| intrinsics_logical.ll | ||
| loads.ll | ||
| mul_ops.ll | ||
| nand.ll | ||
| or_ops.ll | ||
| private.ll | ||
| rotate_ops.ll | ||
| select_bits.ll | ||
| shift_ops.ll | ||
| sp_farith.ll | ||
| stores.ll | ||
| struct_1.ll | ||
| trunc.ll | ||
| vec_const.ll | ||
| vecinsert.ll | ||