llvm-6502/test/CodeGen
Luke Cheeseman 67b17f9ff8 [ARM] - Fix lowering of shufflevectors in AArch32
Some shufflevectors are currently being incorrectly lowered in the AArch32
backend as the existing checks for detecting the NEON operations from the
shufflevector instruction expects the shuffle mask and the vector operands to be
of the same length.

This is not always the case as the mask may be twice as long as the operand;
here only the lower half of the shufflemask gets checked, so provided the lower
half of the shufflemask looks like a vector transpose (or even is just all -1
for undef) then the intrinsics may get incorrectly lowered into a vector
transpose (VTRN) instruction.

This patch fixes this by accommodating for both cases and adds regression tests.

Differential Revision: http://reviews.llvm.org/D11407



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243103 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-24 09:57:05 +00:00
..
AArch64 This patch eanble register coalescing to coalesce the following: 2015-07-23 19:24:53 +00:00
AMDGPU
ARM [ARM] - Fix lowering of shufflevectors in AArch32 2015-07-24 09:57:05 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips
MIR MIR Serialization: Serialize the '.cfi_offset' CFI instruction. 2015-07-23 23:09:07 +00:00
MSP430
NVPTX [BranchFolding] do not iterate the aliases of virtual registers 2015-07-22 04:16:52 +00:00
PowerPC Clean up function attributes on PPC fast-isel tests. 2015-07-24 01:07:50 +00:00
SPARC
SystemZ
Thumb [ARM] Make the frame lowering code ready for shrink-wrapping. 2015-07-22 16:34:37 +00:00
Thumb2 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-21 00:18:59 +00:00
WebAssembly WebAssembly: test that valid -mcpu flags are accepted. 2015-07-23 23:00:04 +00:00
WinEH
X86 fix crash in machine trace metrics due to processing dbg_value instructions (PR24199) 2015-07-23 22:56:53 +00:00
XCore