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cfff317af7
llvm-6502/test/CodeGen
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Elena Demikhovsky cfff317af7 AVX-512: select operation for i1 vectors 
like: select i1 %cond, <16 x i1> %a, <16 x i1> %b.
I added pseudo-CMOV patterns to resolve the "select".
Added tests for KNL and SKX.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237106 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 09:36:52 +00:00
..
AArch64 llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll: s/REQUIRE/REQUIRES/ 2015-05-09 05:59:00 +00:00
ARM Migrate existing backends that care about software floating point 2015-05-12 01:26:05 +00:00
BPF
CPP
Generic Migrate existing backends that care about software floating point 2015-05-12 01:26:05 +00:00
Hexagon [Hexagon] Generate more hardware loops 2015-05-08 20:18:21 +00:00
Inputs
Mips [mips] Emit the .insn directive for empty basic blocks. 2015-05-08 09:10:15 +00:00
MSP430
NVPTX
PowerPC Fix test added in r236850 for OSX builders. 2015-05-08 14:04:54 +00:00
R600
SPARC
SystemZ [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load 2015-05-05 19:34:10 +00:00
Thumb
Thumb2 Thumb2SizeReduction: Check the correct set of registers for LDMIA. 2015-05-05 20:07:10 +00:00
WinEH [WinEH] Handle nested landing pads that return directly to the parent function. 2015-05-11 23:06:02 +00:00
X86 AVX-512: select operation for i1 vectors 2015-05-12 09:36:52 +00:00
XCore