Ruchira Sasanka d33238bb7b --corrected coalescing test: coalsed only if two are of the same reg class ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@729 91177308-0d34-0410-b5e6-96231b3b80d8		2001-10-12 17:48:18 +00:00
..
InstrSched	Add graph edges due to implicit refs in each machine instruction.	2001-10-11 04:22:45 +00:00
InstrSelection	Machine-independent code generation routines used in instruction	2001-10-10 20:50:43 +00:00
LiveVar	added support for implict operands in machine instruction	2001-10-12 17:47:23 +00:00
RegAlloc	--corrected coalescing test: coalsed only if two are of the same reg class	2001-10-12 17:48:18 +00:00
Makefile
SparcV9AsmPrinter.cpp	Add support for new style casts	2001-10-01 16:18:37 +00:00
SparcV9Instr.def	Change latency of setuw and setsw to 2 cycles.	2001-09-30 23:46:57 +00:00
SparcV9InstrSelection.cpp	Record implicitRefs for each machine instruction instead of	2001-10-11 04:23:19 +00:00
SparcV9Internals.h	added suggesting color support	2001-09-30 23:19:57 +00:00
SparcV9RegClassInfo.cpp
SparcV9RegClassInfo.h	--removed %g regs being allocated - fix later	2001-10-09 23:36:13 +00:00
SparcV9RegInfo.cpp	* Both Method & GlobalVariable now subclass GlobalValue	2001-10-03 14:53:21 +00:00
SparcV9RegInfo.h
SparcV9TargetMachine.cpp