Vasileios Kalintiris d72ba1af57 [mips] Optimize code generation for 64-bit variable shift instructions. ... Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235376 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-21 10:49:03 +00:00
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Analysis	Recognize n/1 in the SCEV divide function	2015-04-20 16:03:28 +00:00
Assembler
Bindings
Bitcode	[opaque pointer type] Explicit pointee type for call instruction	2015-04-17 06:40:14 +00:00
BugPoint	bugpoint Enhancement.	2015-04-20 23:42:22 +00:00
CodeGen	[mips] Optimize code generation for 64-bit variable shift instructions.	2015-04-21 10:49:03 +00:00
DebugInfo
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MC	AVX-512: Added logical and arithmetic instructions for SKX	2015-04-21 10:27:40 +00:00
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SymbolRewriter
TableGen	Add support for v1i128 type.	2015-04-17 16:11:05 +00:00
tools	[Mips] Support DT_MIPS_OPTIONS dynamic section tag in the llvm-readobj	2015-04-20 05:34:48 +00:00
Transforms	InstCombine: fold (sitofp (zext x)) to (uitofp x)	2015-04-21 00:05:41 +00:00
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