llvm-6502/include/llvm/CodeGen
Arnaud A. de Grandmaison d736763847 CalcSpillWeights: allow overidding the spill weight normalizing function
This will enable the PBQP register allocator to provide its own normalizing function.

No functionnal change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:56:14 +00:00
..
PBQP include/llvm/CodeGen/PBQP: Update @param(s) in comments. [-Wdocumentation] 2013-11-09 03:54:05 +00:00
Analysis.h
AsmPrinter.h Produce .weak_def_can_be_hidden for some linkonce_odr values 2013-10-30 22:08:11 +00:00
CalcSpillWeights.h CalcSpillWeights: allow overidding the spill weight normalizing function 2013-11-11 19:56:14 +00:00
CallingConvLower.h
CommandFlags.h Speling fixes. 2013-10-22 15:18:03 +00:00
DAGCombine.h
DFAPacketizer.h
EdgeBundles.h
FastISel.h
FunctionLoweringInfo.h
GCMetadata.h
GCMetadataPrinter.h
GCs.h
GCStrategy.h
IntrinsicLowering.h
ISDOpcodes.h [ARM] Use the load-acquire/store-release instructions optimally in AArch32. 2013-09-26 12:22:36 +00:00
JITCodeEmitter.h
LatencyPriorityQueue.h
LexicalScopes.h
LinkAllAsmWriterComponents.h
LinkAllCodegenComponents.h
LiveInterval.h Print register in LiveInterval::print() 2013-10-10 21:29:05 +00:00
LiveIntervalAnalysis.h Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
LiveIntervalUnion.h Rename LiveRange to LiveInterval::Segment 2013-10-10 21:28:43 +00:00
LiveRangeEdit.h
LiveRegMatrix.h
LiveRegUnits.h LiveRegUnits: Use *MBB for consistency and convenience. 2013-10-14 22:18:59 +00:00
LiveStackAnalysis.h
LiveVariables.h
MachineBasicBlock.h Even more spelling fixes for "instruction". 2013-09-28 13:42:22 +00:00
MachineBlockFrequencyInfo.h
MachineBranchProbabilityInfo.h
MachineCodeEmitter.h
MachineCodeInfo.h
MachineConstantPool.h
MachineDominators.h
MachineFrameInfo.h
MachineFunction.h
MachineFunctionAnalysis.h
MachineFunctionPass.h
MachineInstr.h Rename parameter: defined regs are not incoming. 2013-10-10 21:28:38 +00:00
MachineInstrBuilder.h
MachineInstrBundle.h
MachineJumpTableInfo.h
MachineLoopInfo.h
MachineMemOperand.h
MachineModuleInfo.h
MachineModuleInfoImpls.h
MachineOperand.h
MachinePassRegistry.h
MachinePostDominators.h
MachineRegisterInfo.h
MachineRelocation.h
MachineScheduler.h Allow subtarget selection of the default MachineScheduler and document the interface. 2013-09-20 05:14:41 +00:00
MachineSSAUpdater.h
MachineTraceMetrics.h
MachORelocation.h
Passes.h Move the old pass manager infrastructure into a legacy namespace and 2013-11-09 12:26:54 +00:00
PseudoSourceValue.h
RegAllocPBQP.h Re-apply r194300 with fixes for warnings. 2013-11-09 03:08:56 +00:00
RegAllocRegistry.h
RegisterClassInfo.h
RegisterPressure.h Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
RegisterScavenging.h
ResourcePriorityQueue.h
RuntimeLibcalls.h LegalizeDAG: allow libcalls for max/min atomic operations 2013-10-25 09:30:20 +00:00
ScheduleDAG.h Explicitly request unsigned enum types when desired 2013-10-08 20:15:11 +00:00
ScheduleDAGInstrs.h Even more spelling fixes for "instruction". 2013-09-28 13:42:22 +00:00
ScheduleDFS.h
ScheduleHazardRecognizer.h
SchedulerRegistry.h
ScoreboardHazardRecognizer.h
SelectionDAG.h Keep TBAA info when rewriting SelectionDAG loads and stores 2013-10-28 11:17:59 +00:00
SelectionDAGISel.h Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. 2013-10-05 05:38:16 +00:00
SelectionDAGNodes.h Remove an old workaround for a compiler that EOL'd years ago. 2013-09-29 19:39:02 +00:00
SlotIndexes.h
StackMaps.h [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic. 2013-11-08 23:28:16 +00:00
StackProtector.h Reformat code with clang-format. 2013-10-30 02:25:14 +00:00
TargetLoweringObjectFileImpl.h
TargetSchedule.h IfConverter: Use TargetSchedule for instruction latencies 2013-09-30 15:28:56 +00:00
ValueTypes.h Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 2013-10-10 17:00:52 +00:00
ValueTypes.td Implement aarch64 neon instruction set AdvSIMD (Across). 2013-10-05 08:22:10 +00:00
VirtRegMap.h