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llvm-6502/lib/Target/XCore
History
NAKAMURA Takumi 8e1d64666f Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen. 
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 06:38:37 +00:00
..
Disassembler Stop leaking register infos in the disassemblers. 2013-08-03 22:16:16 +00:00
InstPrinter [XCore] Make use of the target independent global address offset folding. 2013-05-04 17:24:33 +00:00
MCTargetDesc Remove the MachineMove class. 2013-05-13 01:16:13 +00:00
TargetInfo Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
CMakeLists.txt Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen. 2013-08-06 06:38:37 +00:00
LLVMBuild.txt Add XCore disassembler. 2012-12-16 17:29:14 +00:00
Makefile Add instruction encodings and disassembly for 1r instructions. 2012-12-16 17:37:34 +00:00
README.txt test commit 2013-07-29 09:23:13 +00:00
XCore.h [XCore] Move lowering of thread local storage to a separate pass. 2013-05-04 17:01:55 +00:00
XCore.td Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission. 2012-12-16 16:20:48 +00:00
XCoreAsmPrinter.cpp Xcore target 2013-08-01 07:52:05 +00:00
XCoreCallingConv.td
XCoreFrameLowering.cpp [XCore] Ensure implicit operands aren't lost on the return instruction. 2013-07-17 10:58:37 +00:00
XCoreFrameLowering.h Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 2013-02-21 20:05:00 +00:00
XCoreInstrFormats.td [XCore] Add missing 2r instructions. 2013-02-17 22:38:05 +00:00
XCoreInstrInfo.cpp DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
XCoreInstrInfo.h DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
XCoreInstrInfo.td [XCore] Whitespace fixes, no functionality change. 2013-07-03 07:49:03 +00:00
XCoreISelDAGToDAG.cpp [XCore] Fix instruction selection for zext, mkmsk instructions. 2013-07-02 14:46:34 +00:00
XCoreISelLowering.cpp XCore target: Fix Vararg handling 2013-08-01 08:29:44 +00:00
XCoreISelLowering.h The getRegForInlineAsmConstraint function should only accept MVT value types. 2013-06-22 18:37:38 +00:00
XCoreLowerThreadLocal.cpp [XCore] Move lowering of thread local storage to a separate pass. 2013-05-04 17:01:55 +00:00
XCoreMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreMachineFunctionInfo.h Sort includes for all of the .h files under the 'lib' tree. These were 2012-12-04 07:12:27 +00:00
XCoreMCInstLower.cpp Update comments to match recommended doxygen style. 2012-12-17 12:13:41 +00:00
XCoreMCInstLower.h Update comments to match recommended doxygen style. 2012-12-17 12:13:41 +00:00
XCoreRegisterInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 21:04:35 +00:00
XCoreRegisterInfo.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 21:04:35 +00:00
XCoreRegisterInfo.td [XCore] The RRegs register class is a superset of GRRegs. 2013-04-04 19:57:46 +00:00
XCoreSelectionDAGInfo.cpp
XCoreSelectionDAGInfo.h
XCoreSubtarget.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreSubtarget.h Sort includes for all of the .h files under the 'lib' tree. These were 2012-12-04 07:12:27 +00:00
XCoreTargetMachine.cpp Remove the MachineMove class. 2013-05-13 01:16:13 +00:00
XCoreTargetMachine.h Switch TargetTransformInfo from an immutable analysis pass that requires 2013-01-07 01:37:14 +00:00
XCoreTargetObjectFile.cpp [XCore] Use static relocation model by default. 2013-05-04 16:40:58 +00:00
XCoreTargetObjectFile.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00

README.txt 

To-do
-----

* Instruction encodings
* Tailcalls
* Investigate loop alignment
* Add builtins