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da32c9eed6
llvm-6502/lib/Target
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Nate Begeman da32c9eed6 Make a new reg class for 64 bit regs that aliases the 32 bit regs. This 
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.

Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG.  Something wll have to be
figured out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23803 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-19 00:05:37 +00:00
..
Alpha This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out 2005-10-09 20:11:35 +00:00
CBackend fix CBackend/2005-09-27-VolatileFuncPtr.ll 2005-09-27 20:52:44 +00:00
IA64 Fix CodeGen/Generic/bool-to-double.ll 2005-10-07 04:50:48 +00:00
PowerPC Make a new reg class for 64 bit regs that aliases the 32 bit regs. This 2005-10-19 00:05:37 +00:00
Skeleton CR registers are not used by this "target" 2005-09-30 06:43:58 +00:00
Sparc silence some warnings 2005-10-05 17:15:09 +00:00
SparcV8 silence some warnings 2005-10-05 17:15:09 +00:00
SparcV9 silence a warning 2005-10-02 16:27:59 +00:00
X86 Remove some dead code now that the dag combiner exists. 2005-10-15 22:08:02 +00:00
Makefile
MRegisterInfo.cpp Rename MRegisterDesc -> TargetRegisterDesc for consistency 2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp Print: 2005-09-07 05:44:14 +00:00
Target.td Pull DAG ISel generation nodes out of the PowerPC backend to where they 2005-10-10 06:00:30 +00:00
TargetData.cpp Update to use the new MathExtras.h support for log2 computation. 2005-08-02 19:26:06 +00:00
TargetFrameInfo.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00
TargetInstrInfo.cpp
TargetMachine.cpp Remove the X86 and PowerPC Simple instruction selectors; their time has 2005-08-18 23:53:15 +00:00
TargetMachineRegistry.cpp 1. Use SubtargetFeatures in llc/lli. 2005-09-01 21:38:21 +00:00
TargetSchedInfo.cpp
TargetSchedule.td Checking in first round of scheduling tablegen files. Not tied in as yet. 2005-10-18 16:23:40 +00:00
TargetSelectionDAG.td add the integer truncate/extension operations 2005-10-14 06:40:20 +00:00
TargetSubtarget.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00