llvm-6502/test/CodeGen
Reed Kotler dabfebb5c6 Expand pseudo/macro BteqzT8SltX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 04:04:26 +00:00
..
AArch64 AArch64: remove ConstantIsland pass & put literals in separate section. 2013-02-15 09:33:43 +00:00
ARM Re-apply r175088 for bug fix 13622: Add paired register support for 2013-02-14 18:10:21 +00:00
CPP
Generic
Hexagon Hexagon: add support for predicate-GPR copies. 2013-02-13 22:56:34 +00:00
MBlaze
Mips Expand pseudo/macro BteqzT8SltX16. 2013-02-18 04:04:26 +00:00
MSP430
NVPTX [NVPTX] Disable vector registers 2013-02-12 14:18:49 +00:00
PowerPC DAGCombiner: Constant folding around pre-increment loads/stores 2013-02-08 21:35:47 +00:00
R600 R600: Do not fold single instruction with more that 3 kcache read 2013-02-14 16:57:19 +00:00
SI
SPARC
Thumb
Thumb2
X86 Force a cpu for test. It failed on atom due to different scheduling decisions. 2013-02-17 18:26:11 +00:00
XCore