Logo
Explore Mirrors Help
Sign In
6502/llvm-6502
Watch 1
Star 0 Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-27 04:18:42 +00:00
Code Issues Projects Releases Wiki Activity
Files
dca83187b7c4465ad6ff8507052223d31c0ea66a
llvm-6502/test/CodeGen
T
History
Bill Schmidt fc7695a653 Fix missing relocation for TLS addressing peephole optimization.
Report and fix due to Kai Nacke.  Testcase update by me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176029 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25 16:44:35 +00:00
..
AArch64
AArch64: remove ConstantIsland pass & put literals in separate section.
2013-02-15 09:33:43 +00:00
ARM
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
2013-02-22 10:01:33 +00:00
CPP
…
Generic
For inline asm:
2013-01-11 18:12:39 +00:00
Hexagon
Hexagon: Expand cttz, ctlz, and ctpop for now.
2013-02-21 19:39:40 +00:00
MBlaze
…
Mips
Expand pseudos/macros for Selt. This is the last of the complex
2013-02-23 03:09:56 +00:00
MSP430
…
NVPTX
[NVPTX] Disable vector registers
2013-02-12 14:18:49 +00:00
PowerPC
Fix missing relocation for TLS addressing peephole optimization.
2013-02-25 16:44:35 +00:00
R600
R600: Fix for Unigine when MachineSched is enabled
2013-02-21 15:06:59 +00:00
SI
Add R600 backend
2012-12-11 21:25:42 +00:00
SPARC
…
Thumb
Fix thumbv5e frame lowering assertion failure.
2013-02-20 12:21:33 +00:00
Thumb2
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
2013-02-22 10:01:33 +00:00
X86
Fix the root cause of PR15348 by correctly handling alignment 0 on
2013-02-25 14:20:21 +00:00
XCore
…
Powered by Gitea Version: 28.2.0 Page: 1109ms Template: 16ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API