Nadav Rotem aec5861bb6 Add vselect target support for targets that do not support blend but do support ... xor/and/or (For example SSE2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8		2011-09-13 19:17:42 +00:00
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Alpha
ARM	Fix mistake in test runline.	2011-09-12 17:32:58 +00:00
Blackfin
CBackend
CellSPU	Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.	2011-09-02 10:05:01 +00:00
CPP
Generic	This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll	2011-09-08 08:43:23 +00:00
MBlaze
Mips	Fix test cases.	2011-09-09 23:14:58 +00:00
MSP430
PowerPC	Split the init.trampoline intrinsic, which currently combines GCC's	2011-09-06 13:37:06 +00:00
PTX
SPARC
SystemZ
Thumb	Disable these tests harder. They're XFAIL'd, but that means they still run, and	2011-09-06 22:08:18 +00:00
Thumb2	Generalize this test's CHECK statements to handle different indvars modes.	2011-09-13 02:46:27 +00:00
X86	Add vselect target support for targets that do not support blend but do support	2011-09-13 19:17:42 +00:00
XCore	Associate a MemOperand with LDWCP nodes introduced during ISel.	2011-09-12 14:43:23 +00:00