David Goodwin dc4bdcdef1 Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8		2009-08-19 16:08:58 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp	PR4737: Fix a nasty bug in load narrowing with non-power-of-two types.	2009-08-19 08:46:10 +00:00
FastISel.cpp
LegalizeDAG.cpp	Be tidy and use a break to exit from a switch block rather than	2009-08-18 23:52:48 +00:00
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp	Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.	2009-08-19 16:08:58 +00:00
ScheduleDAGSDNodes.h
ScheduleDAGSDNodesEmit.cpp	Be more clever about regclasses in ScheduleDAGSDNodes::EmitCopyFromReg.	2009-08-16 17:40:59 +00:00
SelectionDAG.cpp	Needs to check whether unaligned load / store of i64 is legal here.	2009-08-15 23:41:42 +00:00
SelectionDAGBuild.cpp	Remove a bit more cruft from the sjlj moving to a backend pass.	2009-08-17 20:25:04 +00:00
SelectionDAGBuild.h
SelectionDAGISel.cpp
SelectionDAGPrinter.cpp
TargetLowering.cpp