llvm-6502/test/CodeGen/CellSPU
Scott Michel 1a6cdb6b50 CellSPU:
- Fix v2[if]64 vector insertion code before IBM files a bug report.
- Ensure that zero (0) offsets relative to $sp don't trip an assert
  (add $sp, 0 gets legalized to $sp alone, tripping an assert)
- Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60358 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-01 17:56:02 +00:00
..
and_ops.ll Update and_ops.ll according to the recent dagcombiner changes. 2008-04-28 23:26:22 +00:00
call_indirect.ll Un-XFAIL tests now that they're fixed. 2008-11-11 04:44:42 +00:00
call.ll Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stack 2008-10-30 01:51:48 +00:00
ctpop.ll
dg.exp sabre brings to my attention that the 'tr' suffix is also obsolete 2008-05-20 21:00:03 +00:00
dp_farith.ll
eqv.ll
extract_elt.ll CellSPU: test should use shlqby, not shlqbyi 2008-11-25 01:30:37 +00:00
fcmp.ll
fdiv.ll
fneg-fabs.ll
i64ops.ll CellSPU: 2008-11-24 18:20:46 +00:00
icmp8.ll
icmp16.ll APIntify a test which is potentially unsafe otherwise, and fix the 2008-11-30 04:59:26 +00:00
icmp32.ll
immed16.ll
immed32.ll
immed64.ll Add necessary 64-bit support so that gcc frontend compiles (mostly). Current 2008-06-02 22:18:03 +00:00
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
loads.ll CellSPU: 2008-11-21 02:56:16 +00:00
mul_ops.ll
nand.ll
or_ops.ll
rotate_ops.ll Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 2008-08-31 02:59:23 +00:00
select_bits.ll
shift_ops.ll
sp_farith.ll
stores.ll CellSPU: 2008-11-25 17:29:43 +00:00
struct_1.ll
vec_const.ll Un-XFAIL tests now that they're fixed. 2008-11-11 04:44:42 +00:00
vecinsert.ll CellSPU: 2008-12-01 17:56:02 +00:00