Richard Sandiford d50bcb2162 [SystemZ] Register compare-and-branch support ... This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-28 10:41:11 +00:00
..
AArch64	Track IR ordering of SelectionDAG nodes 3/4.	2013-05-25 03:08:10 +00:00
ARM	Track IR ordering of SelectionDAG nodes 4/4.	2013-05-25 03:26:51 +00:00
CPP
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	Track IR ordering of SelectionDAG nodes 4/4.	2013-05-25 03:26:51 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic	2013-05-21 16:51:30 +00:00
PowerPC	Prefer to duplicate PPC Altivec loads when expanding unaligned loads	2013-05-26 18:08:30 +00:00
R600	R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg	2013-05-23 18:26:42 +00:00
SI
SPARC	Also expand 64-bit bitcasts.	2013-05-20 01:01:43 +00:00
SystemZ	[SystemZ] Register compare-and-branch support	2013-05-28 10:41:11 +00:00
Thumb
Thumb2	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
X86	Convert sqrt functions into sqrt instructions when -ffast-math is in effect.	2013-05-27 15:44:35 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00