Chris Lattner e80242a948 X86 doesn't support sextinreg for 8-bit things either. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24631 91177308-0d34-0410-b5e6-96231b3b80d8		2005-12-07 17:59:14 +00:00
..
Alpha	fix divide and remainder	2005-12-06 23:27:39 +00:00
CBackend	do not allow '.' in symbol names	2005-11-10 21:39:29 +00:00
IA64	Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.	2005-12-05 02:34:29 +00:00
PowerPC	Silence another annoying GCC warning	2005-12-06 20:56:18 +00:00
Skeleton	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
Sparc	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV8	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV9	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
X86	X86 doesn't support sextinreg for 8-bit things either.	2005-12-07 17:59:14 +00:00
Makefile
MRegisterInfo.cpp
SubtargetFeature.cpp
Target.td	* Added instruction property hasCtrlDep for those which r/w control-flow	2005-12-04 08:13:17 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSchedule.td
TargetSelectionDAG.td	On some targets (e.g. X86), shift amounts are not the same as the value	2005-12-05 02:37:26 +00:00
TargetSubtarget.cpp