mirror of
https://github.com/c64scene-ar/llvm-6502.git
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953c681473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
4.4 KiB
LLVM
122 lines
4.4 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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; Tests for indirect addressing on SI, which is implemented using dynamic
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; indexing of vectors.
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; CHECK-LABEL: {{^}}extract_w_offset:
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movrels_b32_e32
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define void @extract_w_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = add i32 %in, 1
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%1 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %0
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store float %1, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}extract_wo_offset:
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movrels_b32_e32
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define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %in
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store float %0, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}extract_neg_offset_sgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
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; CHECK: v_movrels_b32_e32 v{{[0-9]}}, v0
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define void @extract_neg_offset_sgpr(i32 addrspace(1)* %out, i32 %offset) {
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entry:
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%index = add i32 %offset, -512
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%value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}extract_neg_offset_vgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: v_readfirstlane_b32
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; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
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; CHECK-NEXT: v_movrels_b32_e32 v{{[0-9]}}, v0
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; CHECK: s_cbranch_execnz
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define void @extract_neg_offset_vgpr(i32 addrspace(1)* %out) {
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entry:
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%id = call i32 @llvm.r600.read.tidig.x() #1
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%index = add i32 %id, -512
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%value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_w_offset:
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movreld_b32_e32
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define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = add i32 %in, 1
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%1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0
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%2 = extractelement <4 x float> %1, i32 2
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store float %2, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_wo_offset:
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movreld_b32_e32
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define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
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%1 = extractelement <4 x float> %0, i32 2
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store float %1, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_neg_offset_sgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
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; CHECK: v_movreld_b32_e32 v0, v{{[0-9]}}
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define void @insert_neg_offset_sgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out, i32 %offset) {
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entry:
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%index = add i32 %offset, -512
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%value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
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store <4 x i32> %value, <4 x i32> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_neg_offset_vgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: v_readfirstlane_b32
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; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
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; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
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; CHECK: s_cbranch_execnz
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define void @insert_neg_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
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entry:
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%id = call i32 @llvm.r600.read.tidig.x() #1
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%index = add i32 %id, -512
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%value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
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store <4 x i32> %value, <4 x i32> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_neg_inline_offset_vgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: v_readfirstlane_b32
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; CHECK: s_add_i32 m0, m0, -{{[0-9]+}}
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; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
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; CHECK: s_cbranch_execnz
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define void @insert_neg_inline_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
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entry:
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%id = call i32 @llvm.r600.read.tidig.x() #1
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%index = add i32 %id, -16
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%value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
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store <4 x i32> %value, <4 x i32> addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #1
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attributes #1 = { nounwind readnone }
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