llvm-6502/lib/Target/PowerPC
Chris Lattner 28b9cc2d13 allow code using mtcrf to assemble
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23107 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26 22:05:54 +00:00
..
.cvsignore
LICENSE.TXT
Makefile Remove support for 64b PPC, it's been broken for a long time. It'll be 2005-08-13 05:59:16 +00:00
PowerPC.td Factor out common .td file chunks. 2004-12-16 16:31:57 +00:00
PowerPCInstrInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PowerPCTargetMachine.h Add Subtarget support to PowerPC. Next up, using it. 2005-08-04 07:12:09 +00:00
PPC32.td Factor out common .td file chunks. 2004-12-16 16:31:57 +00:00
PPC32JITInfo.h update interface 2005-07-22 20:49:37 +00:00
PPC32RegisterInfo.td Split RegisterClass 'Methods' into MethodProtos and MethodBodies 2005-08-19 19:13:20 +00:00
PPC64.td Factor out common .td file chunks. 2004-12-16 16:31:57 +00:00
PPC64RegisterInfo.td Split RegisterClass 'Methods' into MethodProtos and MethodBodies 2005-08-19 19:13:20 +00:00
PPC.h Remove the X86 and PowerPC Simple instruction selectors; their time has 2005-08-18 23:53:15 +00:00
PPCAsmPrinter.cpp Remove operand type 'crbit', since it is no longer used 2005-08-26 22:04:17 +00:00
PPCBranchSelector.cpp Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the 2005-08-24 23:08:16 +00:00
PPCCodeEmitter.cpp Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the 2005-08-24 23:08:16 +00:00
PPCFrameInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrBuilder.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrFormats.td Fix JIT encoding of conditional branches 2005-08-26 04:11:42 +00:00
PPCInstrInfo.cpp Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrInfo.td allow code using mtcrf to assemble 2005-08-26 22:05:54 +00:00
PPCISelDAGToDAG.cpp implement SELECT_CC fully for the DAG->DAG isel! 2005-08-26 21:23:58 +00:00
PPCISelLowering.cpp implement SELECT_CC fully for the DAG->DAG isel! 2005-08-26 21:23:58 +00:00
PPCISelLowering.h implement SELECT_CC fully for the DAG->DAG isel! 2005-08-26 21:23:58 +00:00
PPCISelPattern.cpp Make fsel emission work with both the pattern and dag-dag selectors, by 2005-08-26 20:25:03 +00:00
PPCJITInfo.cpp update interface 2005-07-22 20:49:37 +00:00
PPCJITInfo.h turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) 2005-07-29 23:32:02 +00:00
PPCRegisterInfo.cpp teach getClass what a condition reg is 2005-08-26 21:51:29 +00:00
PPCRegisterInfo.h Now that the simple isels are dead, so is this. 2005-08-19 18:30:39 +00:00
PPCRegisterInfo.td Remove some regs that are not used. 2005-08-22 22:32:13 +00:00
PPCRelocations.h Eliminate tabs and trailing spaces. 2005-07-27 05:53:44 +00:00
PPCSubtarget.cpp Consolidate the GPOpt stuff to all use the Subtarget, instead of still 2005-08-05 22:05:03 +00:00
PPCSubtarget.h Consolidate the GPOpt stuff to all use the Subtarget, instead of still 2005-08-05 22:05:03 +00:00
PPCTargetMachine.cpp Remove the X86 and PowerPC Simple instruction selectors; their time has 2005-08-18 23:53:15 +00:00
PPCTargetMachine.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
README.txt add an idea 2005-08-24 18:15:24 +00:00

TODO:
* gpr0 allocation
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* use stfiwx in float->int
* be able to combine sequences like the following into 2 instructions:
	lis r2, ha16(l2__ZTV4Cell)
	la r2, lo16(l2__ZTV4Cell)(r2)
	addi r2, r2, 8

* Teach LLVM how to codegen this:
unsigned short foo(float a) { return a; }
as:
_foo:
        fctiwz f0,f1
        stfd f0,-8(r1)
        lhz r3,-2(r1)
        blr
not:
_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr


* Support 'update' load/store instructions.  These are cracked on the G5, but
  are still a codesize win.

* Add a custom legalizer for the GlobalAddress node, to move the funky darwin
  stub stuff from the instruction selector to the legalizer (exposing low-level
  operations to the dag for optzn.  For example, we want to codegen this:

        int A = 0;
        void B() { A++; }
  as:
        lis r9,ha16(_A)
        lwz r2,lo16(_A)(r9)
        addi r2,r2,1
        stw r2,lo16(_A)(r9)
  not:
        lis r2, ha16(_A)
        lwz r2, lo16(_A)(r2)
        addi r2, r2, 1
        lis r3, ha16(_A)
        stw r2, lo16(_A)(r3)

* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

===-------------------------------------------------------------------------===

* Codegen this:

   void test2(int X) {
     if (X == 0x12345678) bar();
   }

    as:

       xoris r0,r3,0x1234
       cmpwi cr0,r0,0x5678
       beq cr0,L6

    not:

        lis r2, 4660
        ori r2, r2, 22136 
        cmpw cr0, r3, r2  
        bne .LBB_test2_2

===-------------------------------------------------------------------------===

Lump the constant pool for each function into ONE pic object, and reference
pieces of it as offsets from the start.  For functions like this (contrived
to have lots of constants obviously):

double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }

We generate:

_X:
        lis r2, ha16(.CPI_X_0)
        lfd f0, lo16(.CPI_X_0)(r2)
        lis r2, ha16(.CPI_X_1)
        lfd f2, lo16(.CPI_X_1)(r2)
        fmadd f0, f1, f0, f2
        lis r2, ha16(.CPI_X_2)
        lfd f1, lo16(.CPI_X_2)(r2)
        lis r2, ha16(.CPI_X_3)
        lfd f2, lo16(.CPI_X_3)(r2)
        fmadd f1, f0, f1, f2
        blr

It would be better to materialize .CPI_X into a register, then use immediates
off of the register to avoid the lis's.  This is even more important in PIC 
mode.

===-------------------------------------------------------------------------===