Chris Lattner eb5d47d99d Fix a CQ regression from my patch to split F32/F64 into seperate register ...

classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8

2005-10-07 05:00:52 +00:00

..

Alpha

This is suppose to work now

2005-10-06 16:54:29 +00:00

CBackend

fix CBackend/2005-09-27-VolatileFuncPtr.ll

2005-09-27 20:52:44 +00:00

IA64

Fix CodeGen/Generic/bool-to-double.ll

2005-10-07 04:50:48 +00:00

PowerPC

Fix a CQ regression from my patch to split F32/F64 into seperate register

2005-10-07 05:00:52 +00:00

Skeleton

CR registers are not used by this "target"

2005-09-30 06:43:58 +00:00

Sparc

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV8

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV9

silence a warning

2005-10-02 16:27:59 +00:00

X86

silence some warnings

2005-10-02 16:29:36 +00:00

Makefile

Implement the --enable-targets= feature of the configure script. The make

2005-04-22 17:20:11 +00:00

MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

Print:

2005-09-07 05:44:14 +00:00

Target.td

Add a forward def

2005-10-04 05:09:20 +00:00

TargetData.cpp

Update to use the new MathExtras.h support for log2 computation.

2005-08-02 19:26:06 +00:00

TargetFrameInfo.cpp

Eliminate all remaining tabs and trailing spaces.

2005-07-27 06:12:32 +00:00

TargetInstrInfo.cpp

Convert tabs to spaces

2005-04-22 17:54:37 +00:00

TargetMachine.cpp

Remove the X86 and PowerPC Simple instruction selectors; their time has

2005-08-18 23:53:15 +00:00

TargetMachineRegistry.cpp

1. Use SubtargetFeatures in llc/lli.

2005-09-01 21:38:21 +00:00

TargetSchedInfo.cpp

Convert tabs to spaces

2005-04-22 17:54:37 +00:00

TargetSubtarget.cpp

Eliminate all remaining tabs and trailing spaces.

2005-07-27 06:12:32 +00:00