llvm-6502/test/CodeGen
Derek Schuff 07ffcb1007 [x86 fast-isel] Materialize allocas with the correct-sized lea for ILP32
Summary:
X86FastISel::fastMaterializeAlloca was incorrectly conditioning its
opcode selection on subtarget bitness rather than pointer size.

Differential Revision: http://reviews.llvm.org/D6136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221386 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 19:27:21 +00:00
..
AArch64 [AArch64] Use the correct register class for ORR. 2014-11-04 22:20:07 +00:00
ARM ARM: try to add extra CS-register whenever stack alignment >= 8. 2014-11-05 00:27:20 +00:00
CPP
Generic
Hexagon
Inputs
Mips ps][microMIPS] Implement CodeGen support for ANDI16 instruction 2014-11-05 17:43:00 +00:00
MSP430
NVPTX [NVPTX] Add NVPTXLowerStructArgs pass 2014-11-05 18:19:30 +00:00
PowerPC
R600 R600/SI: Add testcase I forgot to commit from months ago 2014-11-05 19:01:22 +00:00
SPARC
SystemZ
Thumb Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves. 2014-11-05 06:43:02 +00:00
Thumb2
X86 [x86 fast-isel] Materialize allocas with the correct-sized lea for ILP32 2014-11-05 19:27:21 +00:00
XCore