Colin LeMahieu 35e1281ec7 [Hexagon] Adding vector predicate instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227613 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-30 21:24:06 +00:00
..
AArch64
ARM
Hexagon	[Hexagon] Adding vector predicate instructions.	2015-01-30 21:24:06 +00:00
Mips	[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.	2015-01-29 11:33:41 +00:00
PowerPC	[PowerPC] Add assembler support for mcrfs and friends	2015-01-15 01:00:53 +00:00
Sparc
SystemZ
X86	[X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions.	2015-01-28 10:09:56 +00:00
XCore