Colin LeMahieu 35e1281ec7 [Hexagon] Adding vector predicate instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227613 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-30 21:24:06 +00:00
..
AArch64	Update AArch64 ELF relocations to ABI 1.0	2014-11-26 10:49:18 +00:00
ARM	ARM: further correct .fpu directive handling	2015-01-30 19:35:18 +00:00
AsmParser	MC: Don't emit .no_dead_strip on targets which don't support it	2014-12-24 04:11:42 +00:00
COFF	Bring r226038 back.	2015-01-19 15:16:06 +00:00
Disassembler	[Hexagon] Adding vector predicate instructions.	2015-01-30 21:24:06 +00:00
ELF	Revert llvm/test/MC/ELF/noexec.s in r227074, "Fix a problem where the AArch64 ELF assembler was failing with"	2015-01-26 09:30:29 +00:00
Hexagon	[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.	2014-12-09 18:16:49 +00:00
MachO	Add r224985 back with fixes.	2015-01-19 21:11:14 +00:00
Markup
Mips	[mips] Manually replace JAL pseudo-instructions with their JALR equivalent, instead of using InstAlias.	2015-01-30 11:18:50 +00:00
PowerPC	[PowerPC] Add assembler support for mcrfs and friends	2015-01-15 01:00:53 +00:00
R600	R600/SI: Add a stub GCNTargetMachine	2015-01-06 18:00:21 +00:00
Sparc
SystemZ
X86	[x86] Change u8imm operands to always print as unsigned. This makes shuffle masks and the like make way more sense.	2015-01-23 08:00:59 +00:00