Matt Arsenault f1b16047b7 R600/SI: Prefer selecting more e64 instruction forms. ...

Add some more tests to make sure better operand
choices are still made. Leave some cases that seem
to have no reason to ever be e64 alone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217789 91177308-0d34-0410-b5e6-96231b3b80d8

2014-09-15 17:15:02 +00:00

..

AArch64

[FastISel][AArch64] Add support for non-native types for logical ops.

2014-09-13 23:46:28 +00:00

ARM

[ARM] Add Thumb-2 code size optimization regression test for LSR (register).

2014-09-11 10:45:50 +00:00

CPP

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Generic

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Hexagon

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Inputs

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Mips

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MSP430

Drop the W postfix on the 16-bit registers.

2014-09-10 06:58:14 +00:00

NVPTX

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PowerPC

Address comments on r217622

2014-09-12 14:26:36 +00:00

R600

R600/SI: Prefer selecting more e64 instruction forms.

2014-09-15 17:15:02 +00:00

SPARC

Provide an implementation of getNoopForMachoTarget for SPARC.

2014-09-11 17:40:51 +00:00

SystemZ

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Thumb

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Thumb2

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X86

[x86] Begin emitting PBLENDW instructions for integer blend operations

2014-09-15 12:40:54 +00:00

XCore

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