Arnold Schwaighofer f28a29b776 Merge load/store sequences with adresses: base + index + offset ...

We would also like to merge sequences that involve a variable index like in the
example below.

    int index = *idx++
    int i0 = c[index+0];
    int i1 = c[index+1];
    b[0] = i0;
    b[1] = i1;

By extending the parsing of the base pointer to handle dags that contain a
base, index, and offset we can handle examples like the one above.

The dag for the code above will look something like:

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i8 load %index))))

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i32 add (i32 signextend (i8 load %index))
                                         (i32 1)))))

The code that parses the tree ignores the intermediate sign extensions. However,
if there is a sign extension it needs to be on all indexes.

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (add (i8 load %index)
                                     (i8 1))))
 vs

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i32 add (i32 signextend (i8 load %index))
                                         (i32 1)))))
radar://13536387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483 91177308-0d34-0410-b5e6-96231b3b80d8

2013-04-01 18:12:58 +00:00

..

CMakeLists.txt

…

DAGCombiner.cpp

Merge load/store sequences with adresses: base + index + offset

2013-04-01 18:12:58 +00:00

FastISel.cpp

[fast-isel] Add a preemptive fix for the case where we fail to materialize an

2013-03-28 23:04:47 +00:00

FunctionLoweringInfo.cpp

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InstrEmitter.cpp

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InstrEmitter.h

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LegalizeDAG.cpp

Remove default from fully covered switch.

2013-03-08 17:03:19 +00:00

LegalizeFloatTypes.cpp

Set properties for f128 type.

2013-03-01 21:11:44 +00:00

LegalizeIntegerTypes.cpp

Fix PR10475

2013-03-01 18:40:30 +00:00

LegalizeTypes.cpp

Move SDNode order propagation to SDNodeOrdering, which also fixes a missed

2013-03-20 14:51:01 +00:00

LegalizeTypes.h

Move SDNode order propagation to SDNodeOrdering, which also fixes a missed

2013-03-20 14:51:01 +00:00

LegalizeTypesGeneric.cpp

…

LegalizeVectorOps.cpp

SelectionDAG compile time improvement.

2013-02-22 23:33:30 +00:00

LegalizeVectorTypes.cpp

SDAG: Handle scalarizing an extend of a <1 x iN> vector.

2013-03-07 05:47:54 +00:00

LLVMBuild.txt

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Makefile

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ResourcePriorityQueue.cpp

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ScheduleDAGFast.cpp

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ScheduleDAGRRList.cpp

Revert "pre-RA-sched: fix TargetOpcode usage"

2013-03-20 15:43:00 +00:00

ScheduleDAGSDNodes.cpp

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ScheduleDAGSDNodes.h

Fix #includes, so we include only what we really need.

2013-02-20 00:26:25 +00:00

ScheduleDAGVLIW.cpp

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SDNodeDbgValue.h

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SDNodeOrdering.h

Make variable name more explicit and eliminate redundant lookup in SDNodeOrdering

2013-03-20 23:10:59 +00:00

SelectionDAG.cpp

When computing the demanded bits of Load SDNodes, make sure that we are looking at the loaded-value operand and not the ptr result (in case of pre-inc loads).

2013-03-20 22:53:44 +00:00

SelectionDAGBuilder.cpp

Remove the type legality check from the SelectionDAGBuilder when it lowers @llvm.fmuladd to ISD::FMA nodes.

2013-03-23 08:26:53 +00:00

SelectionDAGBuilder.h

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SelectionDAGDumper.cpp

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SelectionDAGISel.cpp

Move SDNode order propagation to SDNodeOrdering, which also fixes a missed

2013-03-20 14:51:01 +00:00

SelectionDAGPrinter.cpp

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TargetLowering.cpp

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TargetSelectionDAGInfo.cpp

…