Jakob Stoklund Olesen f6c690019b Handle REG_SEQUENCE with implicitly defined operands. ... Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136401 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-28 21:38:51 +00:00
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Alpha
ARM	Handle REG_SEQUENCE with implicitly defined operands.	2011-07-28 21:38:51 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips	Lower memory barriers to sync instructions.	2011-07-19 23:30:50 +00:00
MSP430
PowerPC	Add MCObjectFileInfo and sink the MCSections initialization code from	2011-07-20 05:58:47 +00:00
PTX
SPARC
SystemZ	manually upgrade a bunch of tests to modern syntax, and remove some that	2011-06-17 03:14:27 +00:00
Thumb
Thumb2	Introduce MCCodeGenInfo, which keeps information that can affect codegen	2011-07-19 06:37:02 +00:00
X86	Add patterns to generate copies for extract_subvector instead of	2011-07-28 01:26:50 +00:00
XCore	Add intrinsics for the zext / sext instructions.	2011-07-19 13:28:50 +00:00