llvm-6502/test/CodeGen/R600
2013-09-30 18:17:55 +00:00
..
32-bit-local-address-space.ll SelectionDAG: Use correct pointer size when lowering function arguments v2 2013-08-26 15:05:36 +00:00
64bit-kernel-args.ll
128bit-kernel-args.ll
add.ll
address-space.ll Teach CodeGenPrepare about address spaces 2013-09-06 00:18:43 +00:00
and.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
atomic_load_add.ll R600: Add support for local memory atomic add 2013-09-05 18:38:09 +00:00
atomic_load_sub.ll R600: Add support for LDS atomic subtract 2013-09-06 20:17:42 +00:00
bfe_uint.ll
bfi_int.ll
bitcast.ll
build_vector.ll
call_fs.ll
cf_end.ll
complex-folding.ll R600: Move fabs/fneg/sel folding logic into PostProcessIsel 2013-09-12 23:44:44 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
elf.ll
elf.r600.ll
fabs.ll
fadd64.ll
fadd.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fcmp64.ll
fcmp-cnd.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fcmp-cnde-int-args.ll
fcmp.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fconst64.ll
fdiv64.ll
fdiv.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
floor.ll
fma.ll
fmad.ll
fmax.ll R600: Fix handling of NAN in comparison instructions 2013-09-28 02:50:50 +00:00
fmin.ll
fmul64.ll
fmul.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fmuladd.ll
fneg.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fp64_to_sint.ll
fp_to_sint.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fp_to_uint.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
fpext.ll
fptrunc.ll
fsqrt.ll
fsub64.ll
fsub.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
imm.ll
indirect-addressing-si.ll
indirect-addressing.ll
jump-address.ll
kcache-fold.ll R600: Fix handling of NAN in comparison instructions 2013-09-28 02:50:50 +00:00
lds-size.ll R600: Fix incorrect LDS size calculation 2013-09-05 18:37:57 +00:00
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll R600: Move code handling literal folding into R600ISelLowering. 2013-09-12 23:44:53 +00:00
llvm.AMDGPU.barrier.local.ll
llvm.AMDGPU.cube.ll
llvm.AMDGPU.imax.ll
llvm.AMDGPU.imin.ll
llvm.AMDGPU.mul.ll
llvm.AMDGPU.tex.ll
llvm.AMDGPU.trunc.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
llvm.AMDGPU.umax.ll
llvm.AMDGPU.umin.ll
llvm.cos.ll
llvm.floor.ll R600: Expand vector FFLOOR ops 2013-08-16 23:51:29 +00:00
llvm.pow.ll
llvm.rint.ll R600: Expand vector FRINT ops 2013-08-16 23:51:33 +00:00
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll TBAA: update tbaa format from scalar format to struct-path aware format. 2013-09-30 18:17:55 +00:00
llvm.SI.resinfo.ll
llvm.SI.sample.ll
llvm.SI.sampled.ll
llvm.SI.tbuffer.store.ll R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback 2013-09-12 02:55:14 +00:00
llvm.SI.tid.ll
llvm.sin.ll
load64.ll
load-input-fold.ll
load.ll R600/SI: Don't emit S_WQM_B64 instruction for compute shaders 2013-09-05 18:37:52 +00:00
load.vec.ll
local-memory-two-objects.ll R600/SI: Enable local-memory-two-objects lit test 2013-08-27 10:28:26 +00:00
local-memory.ll R600/SI: Don't emit S_WQM_B64 instruction for compute shaders 2013-09-05 18:37:52 +00:00
loop-address.ll
lshl.ll
lshr.ll
mad_int24.ll
mad_uint24.ll
max-literals.ll
mul_int24.ll
mul_uint24.ll
mul.ll
mulhu.ll
or.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
predicates.ll
pv-packing.ll
pv.ll R600: Fix handling of NAN in comparison instructions 2013-09-28 02:50:50 +00:00
r600-encoding.ll
r600cfg.ll
README
reciprocal.ll
rotr.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
rv7x0_count3.ll
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
select.ll R600: Expand SELECT nodes rather than custom lowering them 2013-09-05 18:38:03 +00:00
selectcc-cnd.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
selectcc-cnde-int.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
selectcc-icmp-select-float.ll
selectcc-opt.ll R600: Fix handling of NAN in comparison instructions 2013-09-28 02:50:50 +00:00
set-dx10.ll R600: Fix handling of NAN in comparison instructions 2013-09-28 02:50:50 +00:00
setcc.ll
seto.ll
setuo.ll
sgpr-copy.ll TBAA: update tbaa format from scalar format to struct-path aware format. 2013-09-30 18:17:55 +00:00
shared-op-cycle.ll R600: Use shared op optimization when checking cycle compatibility 2013-09-04 19:53:54 +00:00
shl.ll
short-args.ll
si-lod-bias.ll TBAA: update tbaa format from scalar format to struct-path aware format. 2013-09-30 18:17:55 +00:00
si-vector-hang.ll TBAA: remove !tbaa from testing cases when they are not needed. 2013-09-30 18:17:35 +00:00
sign_extend.ll
sint_to_fp64.ll
sint_to_fp.ll
sra.ll
srl.ll
store.ll TBAA: remove !tbaa from testing cases when they are not needed. 2013-09-30 18:17:35 +00:00
store.r600.ll R600: Change the RAT instruction assembly names so they match the docs 2013-08-16 01:11:46 +00:00
sub.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
swizzle-export.ll
tex-clause-antidep.ll
texture-input-merge.ll
trunc-vector-store-assertion-failure.ll SelectionDAG: Make sure stores are always added to the LegalizedNodes list 2013-08-21 22:42:58 +00:00
trunc.ll R600: Fix i64 to i32 trunc on SI 2013-09-05 19:41:10 +00:00
udiv.ll
uint_to_fp.ll
unsupported-cc.ll R600: Fix handling of NAN in comparison instructions 2013-09-28 02:50:50 +00:00
urecip.ll
urem.ll
vertex-fetch-encoding.ll R600: Add support for v4i32 stores on Cayman 2013-08-16 01:12:00 +00:00
vselect.ll R600: Fix handling of NAN in comparison instructions 2013-09-28 02:50:50 +00:00
vtx-schedule.ll
work-item-intrinsics.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
wrong-transalu-pos-fix.ll TBAA: remove !tbaa from testing cases when they are not needed. 2013-09-30 18:17:35 +00:00
xor.ll R600: Non vector only instruction can be scheduled on trans unit 2013-09-04 19:53:46 +00:00
zero_extend.ll R600: Change the RAT instruction assembly names so they match the docs 2013-08-16 01:11:46 +00:00

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.