Ulrich Weigand 29ec7479a1 [PowerPC] Add target triple to vec_urem_const.ll test case ... This should hopefully fix build bots on other architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214721 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-04 14:55:26 +00:00
..
AArch64	Revert "r214669 - MachineCombiner Pass for selecting faster instruction"	2014-08-04 05:10:33 +00:00
ARM	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon
Inputs
Mips	llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll: Add explicit -mtriple=(mips|mipsel)-linux on 4 lines.	2014-08-01 22:15:38 +00:00
MSP430
NVPTX	[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types	2014-07-23 20:23:49 +00:00
PowerPC	[PowerPC] Add target triple to vec_urem_const.ll test case	2014-08-04 14:55:26 +00:00
R600	R600/SI: Fix extra whitespace in asm str	2014-08-03 05:27:14 +00:00
SPARC	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
X86	[SKX] Enabling load/store instructions: encoding	2014-08-04 14:35:15 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00