Tom Stellard d73d1062fe R600/SI: 64-bit and larger memory access must be at least 4-byte aligned ...

This is true for SI only. CI+ supports unaligned memory accesses,
but this requires driver support, so for now we disallow unaligned
accesses for all GCN targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227822 91177308-0d34-0410-b5e6-96231b3b80d8

2015-02-02 18:02:28 +00:00

..

AArch64

[AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract.

2015-02-02 17:55:57 +00:00

ARM

Fix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0.

2015-02-02 16:56:50 +00:00

BPF

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CPP

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Generic

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Hexagon

[Hexagon] Deleting old variants of intrinsics and adding missing tests.

2015-01-29 17:26:56 +00:00

Inputs

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Mips

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MSP430

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NVPTX

[NVPTX] Emit .pragma "nounroll" for loops marked with nounroll

2015-02-01 02:27:45 +00:00

PowerPC

[PowerPC] VSX stores don't also read

2015-02-01 19:07:41 +00:00

R600

R600/SI: 64-bit and larger memory access must be at least 4-byte aligned

2015-02-02 18:02:28 +00:00

SPARC

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SystemZ

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Thumb

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Thumb2

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X86

fix typo

2015-02-02 17:47:30 +00:00

XCore

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