Devang Patel 2e35047947 Add dominance check for the instruction being hoisted. ... For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-11 18:09:58 +00:00
..
Alpha	Convert more tests over to the new atomic instructions.	2011-09-26 21:30:17 +00:00
ARM	Add dominance check for the instruction being hoisted.	2011-10-11 18:09:58 +00:00
Blackfin
CBackend	Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported	2011-09-26 06:44:27 +00:00
CellSPU	Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.	2011-09-02 10:05:01 +00:00
CPP
Generic	PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval	2011-09-26 06:13:20 +00:00
MBlaze
Mips	Test cases for 64-bit load and store instructions.	2011-10-11 01:52:31 +00:00
MSP430
PowerPC	Convert more tests over to the new atomic instructions.	2011-09-26 21:30:17 +00:00
PTX	PTX: Add new patterns for bitconvert and any_extend	2011-09-29 01:13:12 +00:00
SPARC
SystemZ
Thumb	Reapply r141365 now that PR11107 is fixed.	2011-10-10 22:59:55 +00:00
Thumb2	ARM Darwin default relocation model is PIC.	2011-09-30 17:41:35 +00:00
X86	Add dominance check for the instruction being hoisted.	2011-10-11 18:09:58 +00:00
XCore	Associate a MemOperand with LDWCP nodes introduced during ISel.	2011-09-12 14:43:23 +00:00