Ahmed Bougacha 605c40341b [ARM] Combine base-updating/post-incrementing vector load/stores. ... We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223862 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-10 00:07:37 +00:00
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AArch64	[FastISel][AArch64] Fix a missing nullptr check in 'computeAddress'.	2014-12-09 19:44:38 +00:00
ARM	[ARM] Combine base-updating/post-incrementing vector load/stores.	2014-12-10 00:07:37 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	[PowerPC 4/4] Enable little-endian support for VSX.	2014-12-09 16:59:57 +00:00
R600
SPARC
SystemZ
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X86	[AVX512] Added lowering for VBROADCASTSS/SD instructions.	2014-12-09 18:45:30 +00:00
XCore