mirror of
https://github.com/KarolS/millfork.git
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Reorganize optimizations a bit
This commit is contained in:
Karol Stasiak
parent
a527eea0fc
commit
128dabba3f
@ -264,7 +264,7 @@ object Main {
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val extras = List(
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if (options.flag(CompilationFlag.EmitIllegals)) UndocumentedOptimizations.All else Nil,
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if (options.flag(CompilationFlag.Emit65CE02Opcodes)) CE02Optimizations.All else Nil,
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if (options.flag(CompilationFlag.EmitCmosOpcodes)) CmosOptimizations.All else LaterOptimizations.Nmos,
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if (options.flag(CompilationFlag.EmitCmosOpcodes)) CmosOptimizations.All else NmosOptimizations.All,
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if (options.flag(CompilationFlag.EmitHudsonOpcodes)) HudsonOptimizations.All else Nil,
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if (options.flag(CompilationFlag.EmitEmulation65816Opcodes)) SixteenOptimizations.AllForEmulation else Nil,
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if (options.flag(CompilationFlag.EmitNative65816Opcodes)) SixteenOptimizations.AllForNative else Nil,
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@ -10,6 +10,8 @@ import millfork.node.NiceFunctionProperty
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*/
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object VeryLateM6809AssemblyOptimizations {
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def None(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[MLine]] = Nil
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def All(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[MLine]] = {
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val result = Seq.newBuilder[AssemblyOptimization[MLine]]
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// TODO: add stuff here
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@ -290,54 +290,6 @@ object LaterOptimizations {
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)
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private def incDecThroughIndexRegister(amount: Int, dec: Boolean, carrySet: Boolean, useX: Boolean) = {
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val ldAddrModes = if (useX) LdxAddrModes else LdyAddrModes
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val stAddrModes = if (useX) StxAddrModes else StyAddrModes
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val ldOp = if (useX) LDX else LDY
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val stOp = if (useX) STX else STY
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val changeOp = if (dec) if (useX) DEX else DEY else if (useX) INX else INY
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val addOp = if (dec) SBC else ADC
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val addParam = if (dec ^ carrySet) amount + 1 else amount
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val indexState = if (useX) State.X else State.Y
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val cState = if (carrySet) HasSet(State.C) else HasClear(State.C)
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val carryOp = if (carrySet) SEC else CLC
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(ldAddrModes) & HasClear(State.D)).capture(11) ~
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(Elidable & HasOpcode(carryOp)).? ~
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(Elidable & HasOpcode(addOp) & HasImmediate(addParam) & cState) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(stAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.C, State.V, indexState)).capture(12) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](11).head.copy(opcode = ldOp) ::
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(List.fill(amount)(AssemblyLine.implied(changeOp)) :+
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ctx.get[List[AssemblyLine]](12).head.copy(opcode = stOp))
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}
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}
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val IncrementThroughIndexRegisters = new RuleBasedAssemblyOptimization("Increment through index registers",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = true),
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incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = false),
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incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = true),
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incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = false),
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incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = true),
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incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = false),
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incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = true),
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incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = false),
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incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = true),
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incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = false),
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incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = true),
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incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = false),
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(Elidable & HasOpcode(TYA) & HasClear(State.D)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code =>
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AssemblyLine.implied(INY).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEY).pos(code(2).source) :: code.drop(3)
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},
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(Elidable & HasOpcode(TXA) & HasClear(State.D)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code =>
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AssemblyLine.implied(INX).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEX).pos(code(2).source) :: code.drop(3)
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},
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)
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val LoadingBranchesOptimization = new RuleBasedAssemblyOptimization("Loading branches optimization",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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@ -451,48 +403,6 @@ object LaterOptimizations {
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},
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)
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val UseIndexedX = new RuleBasedAssemblyOptimization("Using indexed-indirect addressing mode",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasAddrMode(IndexedY) & HasX(0) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { code =>
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code.tail.init :+ code.last.copy(addrMode = IndexedX)
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(0xff) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code =>
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code.tail.init ++ List(AssemblyLine.implied(INX), code.last.copy(addrMode = IndexedX))
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(1) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code =>
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code.tail.init ++ List(AssemblyLine.implied(DEX), code.last.copy(addrMode = IndexedX))
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasAddrMode(IndexedY) & MatchX(1) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { (code, ctx)=>
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val lastLine = code.last
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code.tail.init ++ List(lastLine.copy(addrMode = IndexedX, parameter = lastLine.parameter - ctx.get[Int](1)))
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).*.capture(2) ~
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(Elidable & HasAddrMode(IndexedY) & DoesntMatterWhatItDoesWith(State.Y, State.X)).capture(0) ~
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Linear.*.capture(3) ~
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(Elidable & HasOpcode(LDX) & MatchImmediate(1) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~~> { (code, ctx) =>
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val mainLine = ctx.get[List[AssemblyLine]](0).head
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ctx.get[List[AssemblyLine]](2) ++ List(
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code.last,
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mainLine.copy(addrMode = IndexedX, parameter = mainLine.parameter - ctx.get[Int](1))) ++
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ctx.get[List[AssemblyLine]](3)
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},
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)
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val UseBit = new RuleBasedAssemblyOptimization("Using BIT instruction",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage))) ~
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@ -648,10 +558,5 @@ object LaterOptimizations {
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UseXInsteadOfStack,
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UseYInsteadOfStack,
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UseZeropageAddressingMode)
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val Nmos = List(
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IncrementThroughIndexRegisters,
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UseIndexedX
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)
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}
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116
src/main/scala/millfork/assembly/mos/opt/NmosOptimizations.scala
Normal file
116
src/main/scala/millfork/assembly/mos/opt/NmosOptimizations.scala
Normal file
@ -0,0 +1,116 @@
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package millfork.assembly.mos.opt
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import millfork.assembly._
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import millfork.assembly.mos._
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import millfork.assembly.mos.Opcode._
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import AddrMode._
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import millfork.assembly.mos.OpcodeClasses._
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import millfork.env.{Constant, NormalFunction, NumericConstant}
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/**
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* @author Karol Stasiak
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*/
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object NmosOptimizations {
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private val LdxAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageY, AbsoluteY)
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private val LdyAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageX, AbsoluteX)
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private val StxAddrModes = Set(Absolute, ZeroPage, ZeroPageY)
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private val StyAddrModes = Set(Absolute, ZeroPage, ZeroPageX)
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private val StaAddrModes = Set(Absolute, ZeroPage, ZeroPageX, AbsoluteX, IndexedY, IndexedX, AbsoluteY)
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private val CpxyAddrModes = Set(Immediate, Absolute, ZeroPage)
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private def incDecThroughIndexRegister(amount: Int, dec: Boolean, carrySet: Boolean, useX: Boolean) = {
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val ldAddrModes = if (useX) LdxAddrModes else LdyAddrModes
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val stAddrModes = if (useX) StxAddrModes else StyAddrModes
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val ldOp = if (useX) LDX else LDY
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val stOp = if (useX) STX else STY
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val changeOp = if (dec) if (useX) DEX else DEY else if (useX) INX else INY
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val addOp = if (dec) SBC else ADC
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val addParam = if (dec ^ carrySet) amount + 1 else amount
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val indexState = if (useX) State.X else State.Y
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val cState = if (carrySet) HasSet(State.C) else HasClear(State.C)
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val carryOp = if (carrySet) SEC else CLC
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(ldAddrModes) & HasClear(State.D)).capture(11) ~
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(Elidable & HasOpcode(carryOp)).? ~
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(Elidable & HasOpcode(addOp) & HasImmediate(addParam) & cState) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(stAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.C, State.V, indexState)).capture(12) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](11).head.copy(opcode = ldOp) ::
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(List.fill(amount)(AssemblyLine.implied(changeOp)) :+
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ctx.get[List[AssemblyLine]](12).head.copy(opcode = stOp))
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}
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}
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val IncrementThroughIndexRegisters = new RuleBasedAssemblyOptimization("Increment through index registers",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = true),
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incDecThroughIndexRegister(1, dec = false, carrySet = false, useX = false),
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incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = true),
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incDecThroughIndexRegister(1, dec = false, carrySet = true, useX = false),
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incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = true),
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incDecThroughIndexRegister(1, dec = true, carrySet = true, useX = false),
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incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = true),
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incDecThroughIndexRegister(2, dec = false, carrySet = false, useX = false),
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incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = true),
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incDecThroughIndexRegister(2, dec = false, carrySet = true, useX = false),
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incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = true),
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incDecThroughIndexRegister(2, dec = true, carrySet = true, useX = false),
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(Elidable & HasOpcode(TYA) & HasClear(State.D)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code =>
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AssemblyLine.implied(INY).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEY).pos(code(2).source) :: code.drop(3)
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},
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(Elidable & HasOpcode(TXA) & HasClear(State.D)) ~
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(Elidable & HasOpcode(CLC)) ~
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(Elidable & HasOpcode(ADC) & HasImmediate(1) & DoesntMatterWhatItDoesWith(State.C, State.N, State.Z, State.V)) ~~> { code =>
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AssemblyLine.implied(INX).pos(code(2).source) :: code.head :: AssemblyLine.implied(DEX).pos(code(2).source) :: code.drop(3)
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},
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)
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val UseIndexedX = new RuleBasedAssemblyOptimization("Using indexed-indirect addressing mode",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasAddrMode(IndexedY) & HasX(0) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { code =>
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code.tail.init :+ code.last.copy(addrMode = IndexedX)
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(0xff) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code =>
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code.tail.init ++ List(AssemblyLine.implied(INX), code.last.copy(addrMode = IndexedX))
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasOpcodeIn(Set(ISC, DCP, SLO, SRE, RRA, RLA)) & HasAddrMode(IndexedY) & HasX(1) & DoesntMatterWhatItDoesWith(State.Y, State.X)) ~~> { code =>
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code.tail.init ++ List(AssemblyLine.implied(DEX), code.last.copy(addrMode = IndexedX))
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).* ~
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(Elidable & HasAddrMode(IndexedY) & MatchX(1) & DoesntMatterWhatItDoesWith(State.Y)) ~~> { (code, ctx)=>
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val lastLine = code.last
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code.tail.init ++ List(lastLine.copy(addrMode = IndexedX, parameter = lastLine.parameter - ctx.get[Int](1)))
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},
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(Elidable & HasOpcode(LDY) & HasImmediate(0) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~
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(Linear & Not(ConcernsY)).*.capture(2) ~
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(Elidable & HasAddrMode(IndexedY) & DoesntMatterWhatItDoesWith(State.Y, State.X)).capture(0) ~
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Linear.*.capture(3) ~
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(Elidable & HasOpcode(LDX) & MatchImmediate(1) & DoesntMatterWhatItDoesWith(State.Z, State.N)) ~~> { (code, ctx) =>
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val mainLine = ctx.get[List[AssemblyLine]](0).head
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ctx.get[List[AssemblyLine]](2) ++ List(
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code.last,
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mainLine.copy(addrMode = IndexedX, parameter = mainLine.parameter - ctx.get[Int](1))) ++
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ctx.get[List[AssemblyLine]](3)
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},
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)
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val All: List[AssemblyOptimization[AssemblyLine]] = List(
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IncrementThroughIndexRegisters,
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UseIndexedX
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)
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}
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@ -24,7 +24,7 @@ object SuperOptimizer extends AssemblyOptimization[AssemblyLine] {
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if (options.flag(CompilationFlag.EmitCmosOpcodes)) {
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allOptimizers ++= CmosOptimizations.All
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} else {
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allOptimizers ++= LaterOptimizations.Nmos
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allOptimizers ++= NmosOptimizations.All
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}
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if (options.flag(CompilationFlag.EmitEmulation65816Opcodes)) {
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allOptimizers ++= SixteenOptimizations.AllForEmulation
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@ -14,7 +14,7 @@ import millfork.assembly.mos.AddrMode._
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//noinspection ZeroIndexToHead
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object VeryLateMosAssemblyOptimizations {
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val StoresOfImmediatesDifferingByOneViaX = new RuleBasedAssemblyOptimization("",
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val StoresOfImmediatesDifferingByOneViaX = new RuleBasedAssemblyOptimization("Use X to store immediates differing by 1",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(LDA) & HasAddrMode(Immediate) & MatchNumericImmediate(0) & HasIndex8) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(ZeroPage, Absolute) & DoesntMatterWhatItDoesWith(State.A, State.X)) ~
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@ -30,7 +30,7 @@ object VeryLateMosAssemblyOptimizations {
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}
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)
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val StoresOfImmediatesDifferingByOneViaY = new RuleBasedAssemblyOptimization("",
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val StoresOfImmediatesDifferingByOneViaY = new RuleBasedAssemblyOptimization("Use Y to store immediates differing by 1",
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needsFlowInfo = FlowInfoRequirement.BothFlows,
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(Elidable & HasOpcode(LDA) & HasAddrMode(Immediate) & MatchNumericImmediate(0) & HasIndex8) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(ZeroPage, Absolute) & DoesntMatterWhatItDoesWith(State.A, State.Y)) ~
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@ -46,6 +46,8 @@ object VeryLateMosAssemblyOptimizations {
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}
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)
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def None(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[AssemblyLine]] = Nil
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def All(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[AssemblyLine]] = {
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val result = Seq.newBuilder[AssemblyOptimization[AssemblyLine]]
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if (!nice(MosNiceFunctionProperty.DoesntChangeX)){
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@ -10,6 +10,8 @@ import millfork.node.NiceFunctionProperty
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*/
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object VeryLateI80AssemblyOptimizations {
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def None(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[ZLine]] = Nil
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def All(nice: Set[NiceFunctionProperty], options: CompilationOptions): Seq[AssemblyOptimization[ZLine]] = {
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val result = Seq.newBuilder[AssemblyOptimization[ZLine]]
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// TODO: add stuff here
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@ -1,7 +1,7 @@
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package millfork.test.emu
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import millfork.assembly.m6809.opt.M6809OptimizationPresets
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import millfork.assembly.mos.opt.{LaterOptimizations, ZeropageRegisterOptimizations}
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import millfork.assembly.mos.opt.{LaterOptimizations, NmosOptimizations, ZeropageRegisterOptimizations}
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import millfork.assembly.z80.opt.Z80OptimizationPresets
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import millfork.{Cpu, OptimizationPresets}
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@ -16,10 +16,10 @@ object EmuOptimizedInlinedRun extends EmuRun(
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OptimizationPresets.Good ++
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OptimizationPresets.Good ++
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OptimizationPresets.AssOpt ++
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OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
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OptimizationPresets.Good ++ NmosOptimizations.All ++
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ZeropageRegisterOptimizations.All ++
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OptimizationPresets.AssOpt ++
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OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
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OptimizationPresets.Good ++ NmosOptimizations.All ++
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ZeropageRegisterOptimizations.All ++
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OptimizationPresets.AssOpt ++
|
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OptimizationPresets.AssOpt ++
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
package millfork.test.emu
|
||||
|
||||
import millfork.assembly.m6809.opt.M6809OptimizationPresets
|
||||
import millfork.assembly.mos.opt.{LaterOptimizations, ZeropageRegisterOptimizations}
|
||||
import millfork.assembly.mos.opt.{LaterOptimizations, NmosOptimizations, ZeropageRegisterOptimizations}
|
||||
import millfork.assembly.z80.opt.{AlwaysGoodZ80Optimizations, Z80OptimizationPresets}
|
||||
import millfork.{Cpu, OptimizationPresets}
|
||||
|
||||
@ -15,8 +15,8 @@ object EmuOptimizedRun extends EmuRun(
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
OptimizationPresets.Good ++
|
||||
OptimizationPresets.Good ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ NmosOptimizations.All ++
|
||||
OptimizationPresets.Good ++ NmosOptimizations.All ++
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
OptimizationPresets.Good ++
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
@ -47,8 +47,8 @@ object EmuSizeOptimizedRun extends EmuRun(
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
OptimizationPresets.Good ++
|
||||
OptimizationPresets.Good ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ NmosOptimizations.All ++
|
||||
OptimizationPresets.Good ++ NmosOptimizations.All ++
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
OptimizationPresets.Good ++
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
@ -66,8 +66,8 @@ object EmuOptimizedSoftwareStackRun extends EmuRun(
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
OptimizationPresets.Good ++
|
||||
OptimizationPresets.Good ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ NmosOptimizations.All ++
|
||||
OptimizationPresets.Good ++ NmosOptimizations.All ++
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
OptimizationPresets.Good ++
|
||||
ZeropageRegisterOptimizations.All ++
|
||||
|
||||
@ -222,7 +222,7 @@ class EmuRun(cpu: millfork.Cpu.Value, nodeOptimizations: List[NodeOptimization],
|
||||
val env2 = new Environment(None, "", CpuFamily.M6502, options)
|
||||
env2.collectDeclarations(program, options)
|
||||
val assembler = new MosAssembler(program, env2, platform)
|
||||
val output = assembler.assemble(callGraph, assemblyOptimizations, options, VeryLateMosAssemblyOptimizations.All)
|
||||
val output = assembler.assemble(callGraph, assemblyOptimizations, options, if (assemblyOptimizations.nonEmpty) VeryLateMosAssemblyOptimizations.All else VeryLateMosAssemblyOptimizations.None)
|
||||
println(";;; compiled: -----------------")
|
||||
output.asm.takeWhile(s => !(s.startsWith(".") && s.contains("= $"))).filterNot(_.contains("; DISCARD_")).foreach(println)
|
||||
println(";;; ---------------------------")
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
package millfork.test.emu
|
||||
|
||||
import millfork.assembly.mos.opt.{LaterOptimizations, UndocumentedOptimizations}
|
||||
import millfork.assembly.mos.opt.{NmosOptimizations, UndocumentedOptimizations}
|
||||
import millfork.{Cpu, OptimizationPresets}
|
||||
|
||||
/**
|
||||
@ -9,13 +9,13 @@ import millfork.{Cpu, OptimizationPresets}
|
||||
object EmuUndocumentedRun extends EmuRun(
|
||||
Cpu.Ricoh, // not Cpu.Mos, because I haven't found an emulator that supports both illegals and decimal mode yet
|
||||
OptimizationPresets.NodeOpt,
|
||||
OptimizationPresets.AssOpt ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.AssOpt ++ NmosOptimizations.All ++
|
||||
UndocumentedOptimizations.All ++
|
||||
OptimizationPresets.Good ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.Good ++ NmosOptimizations.All ++
|
||||
UndocumentedOptimizations.All ++
|
||||
OptimizationPresets.AssOpt ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.AssOpt ++ NmosOptimizations.All ++
|
||||
UndocumentedOptimizations.All ++
|
||||
OptimizationPresets.AssOpt ++ LaterOptimizations.Nmos ++
|
||||
OptimizationPresets.AssOpt ++ NmosOptimizations.All ++
|
||||
UndocumentedOptimizations.All ++
|
||||
OptimizationPresets.Good) {
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user