Sam M W
0f1c01ce60
implement stz
2024-04-24 14:51:43 +01:00
Sam M W
df51b077e7
add/implement BRA instruction for CMOS
2024-04-24 14:51:43 +01:00
Sam M W
4847744518
correction to comment
2024-04-24 14:51:08 +01:00
Matthias Endler
11d9540729
fix typo
2024-04-24 15:41:25 +02:00
Sam M W
54dd0cd536
rename IndirectWithFix to Indirect
2024-04-24 15:41:25 +02:00
Sam M W
ad622bc930
formatting
2024-04-24 15:41:25 +02:00
Sam M W
97d6b3fd89
split the Indirect addressing mode into BuggyIndirect and IndirectWithFix
2024-04-24 15:41:25 +02:00
Sam M W
da30c8c67d
change arr_to_addr to address_from_bytes
2024-04-24 15:41:25 +02:00
omarandlorraine
11499b6bc8
Starting on implementing different variants ( #88 )
...
* start on separating 6502 variants from cpu itself
* add a single variant: the NMOS one
* get examples & tests running again
* Add the Revision A variant, one that has no ROR
* disable failing lint in build-time dependencies
* Variant with no decimal mode
* Revert "disable failing lint in build-time dependencies"
This reverts commit c87975e937
.
* some doc comments
* specify the variant in unit test now the API has changed
---------
Co-authored-by: Sam M W <you@example.com>
2023-10-31 16:45:15 +01:00
omarandlorraine
b52e47bbb5
Fix the PHP opcode ( #92 )
...
* unit test for php
* get test passing
---------
Co-authored-by: Sam M W <you@example.com>
2023-10-30 02:22:37 +01:00
omarandlorraine
6ce85db45c
boring crate related maintenance ( #95 )
...
* remove Cargo.lock
* remove num
---------
Co-authored-by: Sam M W <you@example.com>
2023-10-30 02:20:46 +01:00
omarandlorraine
aa1a47a76f
Fix addition and subtraction ( #72 )
...
* extract decimal logic into separate function
* squash me
* I think we should be doing unsigned arithmetic here
* squash me
* remove unused function
* update the sign checks
* cargo fmt
* get tests to compile again
* get tests passing again
* squash me
* remove pointless conversion from u8 to u8
* cargo fmt
* accumulator is now u8
* add adc test from solid65
* pass the new test
---------
Co-authored-by: Sam M W <you@example.com>
2023-06-29 12:13:49 +02:00
omarandlorraine
849f891e24
Merge pull request #67 from mre/rts
...
Implementation of RTS
2023-04-16 07:08:25 +01:00
Sam M W
bd1ab13dc1
point INY instruction at the correct register
2023-04-15 21:47:17 +01:00
Sam M W
f0fc9829db
PLA opcode should update the flags
2023-04-15 21:44:05 +01:00
Sam M W
26a2f51bc6
don't overshoot the stack pointer! (pla and plp)
2023-04-15 21:37:47 +01:00
Sam M W
62424070a1
disable interrupts after BRK instruction
2023-04-15 21:34:07 +01:00
Sam M W
a8d53f926d
implement BRK
2023-04-15 21:17:28 +01:00
Sam M W
1c31a73a2b
correct endianness for program counter push
2023-04-15 21:01:08 +01:00
Sam M W
239992ea6c
first stab at implementing the JSR instruction
2023-04-15 20:58:31 +01:00
Sam M W
70e85a2eaf
bugfix for the bit opcode
2023-04-15 16:42:05 +01:00
Sam M W
8e797b70fa
implement BNE
2023-04-15 16:17:51 +01:00
Sam M W
18164c7abf
implement RTI as well
2023-04-15 15:36:53 +01:00
Sam M W
1b90243738
implementation of RTS
2023-04-15 15:36:43 +01:00
Sam M W
9f75d1a6b5
the get_byte method needs to take mutable reference to self
...
the reson for this is it's possible for external hardware to have some
side effect on a read.
2023-04-03 22:46:46 +01:00
Sam M W
d2043dc6fb
less verbosity, more expliciteness
2023-04-03 21:07:06 +01:00
Sam M W
7222388c5e
get rid of silly xextend function; just use the .into()
2023-04-03 21:00:17 +01:00
Sam M W
3accd8ce40
as clippy suggests, convert from bool to u8/i8
2023-04-03 07:39:30 +01:00
Sam M W
0708a1084c
fix the tests back up
2023-04-03 07:39:18 +01:00
Sam M W
12c901e8aa
generic argument for CPU represents memory
2023-04-03 07:02:32 +01:00
Sam M W
a8dac6e805
extract memory functionality into a trait
2023-04-03 06:59:40 +01:00
Sam M W
f3f15de8cc
remove memory.get_slice
...
real hardware won't have the ability to dive in and grab a slice from
memory
2023-04-03 05:50:13 +01:00
Sam M W
131b0f312d
remove get_byte_mut_ref method from Memory
...
This is the right thing to do, because the actual hardware will perform
a read and then perform a write. This could have observable side effects
on a real system
2023-04-03 05:50:06 +01:00
omarandlorraine
61b8dfe1f2
add single_step function ( #62 )
...
Co-authored-by: Sam M W <you@example.com>
2023-03-27 00:27:44 +02:00
Matthias Endler
c3438c14e7
Make code more idiomatic ( #61 )
2023-03-20 14:11:44 +01:00
Sam M W
c2e77b5f52
also test subtractions
2022-10-23 07:05:08 +01:00
Sam M W
2bcbfa63b5
fix panic
2022-10-23 07:05:04 +01:00
Sam M W
bf543e2fbe
add failing test
2022-10-23 07:04:52 +01:00
omarandlorraine
32f925feb2
Merge branch 'master' into incdec
2022-10-21 09:10:18 +01:00
Sam M W
f821dce70f
do increments in the same way
2022-10-21 06:45:40 +01:00
Sam M W
e4aebb9dfe
cargo fmt
2022-10-21 06:42:27 +01:00
Sam M W
4e057a2a94
remove unused function decrement_memory
2022-10-21 06:40:56 +01:00
Sam M W
1d0fd6aad0
remove unused function dec_x
2022-10-21 06:37:41 +01:00
Sam M W
7500e8816e
cargo clippy --fix
2022-10-21 06:34:42 +01:00
Sam M W
95731752ba
using the associated function decrement
2022-10-21 06:33:51 +01:00
Sam M W
665ee4193d
x and y are now unsigned and there's less casting all over
2022-10-20 09:42:17 +01:00
Sam M W
41b9b19be2
decrement_y_test passes
2022-10-20 09:32:51 +01:00
Sam M W
c406965560
decrement_x_test passes
2022-10-20 09:23:58 +01:00
Sam M W
1972a42adc
some failing tests
2022-10-20 09:04:44 +01:00
Sam M W
894e4304ea
test branch_across_end_of_address_space
2022-10-18 14:55:22 +01:00