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Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_27
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element epcq_controller_0
{
datum _sortIndex
{
Timer and SPI added.
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value = "8";
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type = "int";
}
}
element epcq_controller_0.avl_csr
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
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value = "8523808";
Initial public release (FW 0.64)
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type = "String";
}
}
element epcq_controller_0.avl_mem
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element i2c_opencores_0
{
datum _sortIndex
{
Timer and SPI added.
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value = "9";
Initial public release (FW 0.64)
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type = "int";
}
}
element i2c_opencores_0.avalon_slave_0
{
datum baseAddress
{
Timer and SPI added.
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value = "8523872";
Initial public release (FW 0.64)
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type = "String";
}
}
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
element i2c_opencores_1
{
datum _sortIndex
{
value = "10";
type = "int";
}
}
element i2c_opencores_1.avalon_slave_0
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
value = "8523840";
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
type = "String";
}
}
Initial public release (FW 0.64)
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element jtag_uart_0
{
datum _sortIndex
{
Timer and SPI added.
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value = "7";
Initial public release (FW 0.64)
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type = "int";
}
}
element jtag_uart_0.avalon_jtag_slave
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
value = "8524000";
Initial public release (FW 0.64)
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type = "String";
}
}
element nios2_hw_crc32_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element nios2_qsys_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element nios2_qsys_0.debug_mem_slave
{
datum baseAddress
{
value = "8521728";
type = "String";
}
}
element nios_custom_instr_bitswap_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element nios_custom_instr_endianconverter_0
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element onchip_memory2_0
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element onchip_memory2_0.s1
{
datum baseAddress
{
value = "8454144";
type = "String";
}
}
element pio_0
{
datum _sortIndex
{
Timer and SPI added.
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value = "11";
Initial public release (FW 0.64)
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type = "int";
}
}
element pio_0.s1
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
value = "8523984";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "String";
}
}
element pio_1
{
datum _sortIndex
{
Timer and SPI added.
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value = "12";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "int";
}
}
element pio_1.s1
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
value = "8523968";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "String";
}
}
element pio_2
{
datum _sortIndex
{
Timer and SPI added.
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value = "13";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "int";
}
}
element pio_2.s1
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
value = "8523952";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "String";
}
}
element pio_3
{
datum _sortIndex
{
Timer and SPI added.
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value = "14";
Initial public release (FW 0.64)
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type = "int";
}
}
element pio_3.s1
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
value = "8523936";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "String";
}
}
element pio_4
{
datum _sortIndex
{
Timer and SPI added.
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value = "15";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "int";
}
}
element pio_4.s1
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
{
datum baseAddress
{
value = "8523920";
type = "String";
}
}
element pio_5
{
datum _sortIndex
{
value = "16";
type = "int";
}
}
element pio_5.s1
Initial public release (FW 0.64)
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{
datum baseAddress
{
Timer and SPI added.
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value = "8523904";
type = "String";
}
}
element timer_0
{
datum _sortIndex
{
value = "6";
type = "int";
}
}
element timer_0.s1
{
datum baseAddress
{
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
value = "8523776";
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE15E22C8" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="ossc.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_27.clk_in" type="clock" dir="end" />
<interface
name="i2c_opencores_0_export"
internal="i2c_opencores_0.export"
type="conduit"
dir="end" />
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
<interface
name="i2c_opencores_1_export"
internal="i2c_opencores_1.export"
type="conduit"
dir="end" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<interface
name="pio_0_sys_ctrl_out"
internal="pio_0.external_connection"
type="conduit"
dir="end" />
<interface
name="pio_1_controls_in"
internal="pio_1.external_connection"
type="conduit"
dir="end" />
<interface
name="pio_2_horizontal_info_out"
internal="pio_2.external_connection"
type="conduit"
dir="end" />
<interface
name="pio_3_vertical_info_out"
internal="pio_3.external_connection"
type="conduit"
dir="end" />
<interface
name="pio_4_linecount_in"
internal="pio_4.external_connection"
type="conduit"
dir="end" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<interface
Misc updates * Fix mask placement and make its brightness adjustable * Line4x
2017-01-23 22:18:15 +00:00
name="pio_5_horizontal_info2_out"
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
internal="pio_5.external_connection"
type="conduit"
dir="end" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<interface name="reset" internal="clk_27.clk_in_reset" type="reset" dir="end" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<module name="clk_27" kind="clock_source" version="16.1" enabled="1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="clockFrequency" value="27000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
name="epcq_controller_0"
kind="altera_epcq_controller_mod"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
enabled="1">
<parameter name="CHIP_SELS" value="1" />
<parameter name="DDASI" value="0" />
<parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="FLASH_TYPE" value="EPCS64" />
<parameter name="IO_MODE" value="STANDARD" />
<parameter name="clkFreq" value="27000000" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
</module>
<module
name="i2c_opencores_0"
kind="i2c_opencores"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
enabled="1">
Add dedicated SPI mode option to i2c_opencores.
2016-11-05 13:39:36 +00:00
<parameter name="dedicated_spi" value="0" />
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
</module>
<module
name="i2c_opencores_1"
kind="i2c_opencores"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
enabled="1">
Add dedicated SPI mode option to i2c_opencores.
2016-11-05 13:39:36 +00:00
<parameter name="dedicated_spi" value="1" />
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
</module>
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<module
name="jtag_uart_0"
kind="altera_avalon_jtag_uart"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
enabled="1">
<parameter name="allowMultipleConnections" value="false" />
<parameter name="avalonSpec" value="2.0" />
<parameter name="clkFreq" value="27000000" />
<parameter name="hubInstanceID" value="0" />
<parameter name="readBufferDepth" value="64" />
<parameter name="readIRQThreshold" value="8" />
<parameter name="simInputCharacterStream" value="" />
<parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
Release 0.73 * Fixed adv. timing tweaker using previous values when updating parameters * Added "Hsync tolerance" option to fix detection of certain Neo-Geo models
2016-09-05 17:49:41 +00:00
<parameter name="useRegistersForReadBuffer" value="true" />
<parameter name="useRegistersForWriteBuffer" value="true" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="useRelativePathForSimFile" value="false" />
<parameter name="writeBufferDepth" value="64" />
<parameter name="writeIRQThreshold" value="8" />
</module>
<module
name="nios2_hw_crc32_0"
kind="nios2_hw_crc32"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
enabled="1">
<parameter name="crc_width" value="32" />
<parameter name="polynomial" value="79764919" />
<parameter name="polynomial_inital" value="4294967295" />
<parameter name="reflected_input" value="1" />
<parameter name="reflected_output" value="1" />
<parameter name="xor_output" value="4294967295" />
</module>
<module
name="nios2_qsys_0"
kind="altera_nios2_gen2"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="EP4CE15E22C8" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave">nios2_qsys_0.jtag_debug_module</parameter>
<parameter name="cdx_enabled" value="false" />
<parameter name="clockFrequency" value="27000000" />
<parameter name="cpuArchRev" value="1" />
<parameter name="cpuID" value="0" />
<parameter name="cpuReset" value="false" />
<parameter name="customInstSlavesSystemInfo"><![CDATA[<info><slave name="nios2_hw_crc32_0" baseAddress="0" addressSpan="8" clockCycleType="VARIABLE" /><slave name="nios_custom_instr_endianconverter_0" baseAddress="8" addressSpan="1" clockCycleType="COMBINATORIAL" /><slave name="nios_custom_instr_bitswap_0" baseAddress="9" addressSpan="1" clockCycleType="COMBINATORIAL" /></info>]]></parameter>
<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
<parameter name="dataAddrWidth" value="24" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer_0.s1' start='0x821000' end='0x821020' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821020' end='0x821040' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821040' end='0x821060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_5.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_4.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210D0' end='0x8210E0' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x8210E0' end='0x8210E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
<parameter name="data_master_paddr_size" value="0" />
<parameter name="dcache_bursts" value="false" />
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dcache_size" value="0" />
<parameter name="dcache_tagramBlockType" value="Automatic" />
<parameter name="dcache_victim_buf_impl" value="ram" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="debug_datatrigger" value="0" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="debug_enabled" value="true" />
<parameter name="debug_hwbreakpoint" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="debug_traceStorage" value="onchip_trace" />
<parameter name="debug_traceType" value="none" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="deviceFamilyName" value="Cyclone IV E" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="dividerType" value="no_div" />
<parameter name="exceptionOffset" value="32" />
<parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
<parameter name="faAddrWidth" value="1" />
<parameter name="faSlaveMapParam" value="" />
<parameter name="fa_cache_line" value="2" />
<parameter name="fa_cache_linesize" value="0" />
<parameter name="flash_instruction_master_paddr_base" value="0" />
<parameter name="flash_instruction_master_paddr_size" value="0" />
<parameter name="icache_burstType" value="None" />
<parameter name="icache_numTCIM" value="0" />
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="icache_size" value="0" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Tiny" />
<parameter name="instAddrWidth" value="24" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="instruction_master_paddr_size" value="0" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="internalIrqMaskSystemInfo" value="31" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="io_regionbase" value="0" />
<parameter name="io_regionsize" value="0" />
<parameter name="master_addr_map" value="false" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
<parameter name="mmu_TLBMissExcSlave" value="None" />
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
<parameter name="mmu_enabled" value="false" />
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="mmu_ramBlockType" value="Automatic" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="mpu_enabled" value="false" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="mpx_enabled" value="false" />
<parameter name="mul_32_impl" value="2" />
<parameter name="mul_64_impl" value="0" />
<parameter name="mul_shift_choice" value="0" />
<parameter name="ocimem_ramBlockType" value="Automatic" />
<parameter name="ocimem_ramInit" value="false" />
<parameter name="regfile_ramBlockType" value="Automatic" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<parameter name="register_file_por" value="false" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="resetOffset" value="0" />
<parameter name="resetSlave" value="onchip_memory2_0.s1" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="setting_activateTrace" value="true" />
<parameter name="setting_allow_break_inst" value="false" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_asic_add_scan_mode_input" value="false" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_asic_third_party_synthesis" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="setting_branchpredictiontype" value="Dynamic" />
<parameter name="setting_breakslaveoveride" value="false" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="setting_dc_ecc_present" value="false" />
<parameter name="setting_disable_tmr_inj" value="false" />
<parameter name="setting_disableocitrace" value="false" />
<parameter name="setting_dtcm_ecc_present" value="false" />
<parameter name="setting_ecc_present" value="false" />
<parameter name="setting_ecc_sim_test_ports" value="false" />
<parameter name="setting_exportHostDebugPort" value="false" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="setting_exportdebuginfo" value="false" />
<parameter name="setting_exportvectors" value="false" />
<parameter name="setting_fast_register_read" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="setting_itcm_ecc_present" value="false" />
<parameter name="setting_mmu_ecc_present" value="true" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="setting_oci_version" value="1" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="setting_removeRAMinit" value="false" />
<parameter name="setting_rf_ecc_present" value="true" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="setting_support31bitdcachebypass" value="true" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<parameter name="setting_tmr_output_disable" value="false" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="setting_usedesignware" value="false" />
<parameter name="shift_rot_impl" value="1" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
<parameter name="tmr_enabled" value="false" />
<parameter name="tracefilename" value="" />
<parameter name="userDefinedSettings" value="" />
</module>
<module
name="nios_custom_instr_bitswap_0"
kind="altera_nios_custom_instr_bitswap"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
enabled="1" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<module
name="nios_custom_instr_endianconverter_0"
kind="altera_nios_custom_instr_endianconverter"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
enabled="1">
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
</module>
<module
name="onchip_memory2_0"
kind="altera_avalon_onchip_memory2"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<parameter name="dataWidth2" value="32" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="deviceFamily" value="Cyclone IV E" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPOR
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="dualPort" value="false" />
<parameter name="ecc_enabled" value="false" />
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<parameter name="enPRInitMode" value="false" />
<parameter name="enableDiffWidth" value="false" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="memorySize" value="40960" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<module name="pio_0" kind="altera_avalon_pio" version="16.1" enabled="1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="27000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="8" />
</module>
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<module name="pio_1" kind="altera_avalon_pio" version="16.1" enabled="1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="27000000" />
<parameter name="direction" value="Input" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<module name="pio_2" kind="altera_avalon_pio" version="16.1" enabled="1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="27000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<module name="pio_3" kind="altera_avalon_pio" version="16.1" enabled="1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="27000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<module name="pio_4" kind="altera_avalon_pio" version="16.1" enabled="1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="27000000" />
<parameter name="direction" value="Input" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<module name="pio_5" kind="altera_avalon_pio" version="16.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="27000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
</module>
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<module name="timer_0" kind="altera_avalon_timer" version="16.1" enabled="1">
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
<parameter name="period" value="1" />
<parameter name="periodUnits" value="USEC" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
<parameter name="systemFrequency" value="27000000" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="watchdogPulse" value="2" />
</module>
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x008210e0" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
end="i2c_opencores_0.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="baseAddress" value="0x00821060" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
start="nios2_qsys_0.data_master"
end="i2c_opencores_1.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x00821040" />
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
end="epcq_controller_0.avl_csr">
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x00821020" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
end="epcq_controller_0.avl_mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
end="nios2_qsys_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00820800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00810000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
end="pio_0.s1">
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x008210d0" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
end="pio_1.s1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x008210c0" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
end="pio_2.s1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x008210b0" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
end="pio_3.s1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x008210a0" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.data_master"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
end="pio_4.s1">
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x00821090" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Timer and SPI added.
2016-10-16 09:53:54 +00:00
start="nios2_qsys_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<parameter name="baseAddress" value="0x00821000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="16.1"
start="nios2_qsys_0.data_master"
end="pio_5.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00821080" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.instruction_master"
end="nios2_qsys_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00820800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.instruction_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00810000" />
<parameter name="defaultConnection" value="false" />
</connection>
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
<connection kind="clock" version="16.1" start="clk_27.clk" end="nios2_qsys_0.clk" />
<connection kind="clock" version="16.1" start="clk_27.clk" end="jtag_uart_0.clk" />
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_0.clk" />
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_1.clk" />
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_2.clk" />
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_3.clk" />
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_4.clk" />
<connection kind="clock" version="16.1" start="clk_27.clk" end="timer_0.clk" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_5.clk" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="clock"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk"
end="onchip_memory2_0.clk1" />
<connection
kind="clock"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk"
end="i2c_opencores_0.clock" />
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
<connection
kind="clock"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
start="clk_27.clk"
end="i2c_opencores_1.clock" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="clock"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk"
end="epcq_controller_0.clock_sink" />
<connection
kind="interrupt"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.irq"
end="i2c_opencores_0.interrupt_sender">
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="irqNumber" value="3" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
</connection>
<connection
kind="interrupt"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.irq"
end="epcq_controller_0.interrupt_sender">
Timer and SPI added.
2016-10-16 09:53:54 +00:00
<parameter name="irqNumber" value="2" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
</connection>
<connection
kind="interrupt"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.irq"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
end="i2c_opencores_1.interrupt_sender">
<parameter name="irqNumber" value="4" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
</connection>
<connection
kind="interrupt"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Timer and SPI added.
2016-10-16 09:53:54 +00:00
start="nios2_qsys_0.irq"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
end="jtag_uart_0.irq">
<parameter name="irqNumber" value="1" />
Timer and SPI added.
2016-10-16 09:53:54 +00:00
</connection>
<connection
kind="interrupt"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Timer and SPI added.
2016-10-16 09:53:54 +00:00
start="nios2_qsys_0.irq"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
end="timer_0.irq">
<parameter name="irqNumber" value="0" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
</connection>
<connection
kind="nios_custom_instruction"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.custom_instruction_master"
end="nios2_hw_crc32_0.nios_custom_instruction_slave">
<parameter name="CIName" value="nios2_hw_crc32_0" />
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0" />
</connection>
<connection
kind="nios_custom_instruction"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.custom_instruction_master"
end="nios_custom_instr_endianconverter_0.s1">
<parameter name="CIName">nios_custom_instr_endianconverter_0</parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="8" />
</connection>
<connection
kind="nios_custom_instruction"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="nios2_qsys_0.custom_instruction_master"
end="nios_custom_instr_bitswap_0.s1">
<parameter name="CIName">nios_custom_instr_bitswap_0</parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="9" />
</connection>
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="i2c_opencores_0.clock_reset" />
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
SD SPI implementation finished
2016-10-20 22:19:53 +00:00
start="clk_27.clk_reset"
end="i2c_opencores_1.clock_reset" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="nios2_qsys_0.reset" />
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="jtag_uart_0.reset" />
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="pio_0.reset" />
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="pio_1.reset" />
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="pio_2.reset" />
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="pio_3.reset" />
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="pio_4.reset" />
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
Timer and SPI added.
2016-10-16 09:53:54 +00:00
end="epcq_controller_0.reset" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
Timer and SPI added.
2016-10-16 09:53:54 +00:00
end="timer_0.reset" />
Improve lo-res mode processing features * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
2017-01-22 22:56:17 +00:00
<connection
kind="reset"
version="16.1"
start="clk_27.clk_reset"
end="pio_5.reset" />
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
<connection
kind="reset"
Update to Quartus 16.1.
2016-12-13 18:55:10 +00:00
version="16.1"
Initial public release (FW 0.64)
2016-02-22 23:03:50 +00:00
start="clk_27.clk_reset"
end="onchip_memory2_0.reset1" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>