ossc/rtl/pll_2x.qip

set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]
Initial public release (FW 0.64) 2016-02-22 23:03:50 +00:00			`set_global_assignment -name IP_TOOL_NAME "ALTPLL"`
update to Quartus 17.1 2017-12-07 19:35:08 +00:00			`set_global_assignment -name IP_TOOL_VERSION "17.1"`
Initial public release (FW 0.64) 2016-02-22 23:03:50 +00:00			`set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"`
			`set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]`
optimize clock network * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl 2019-10-05 21:26:50 +00:00			`set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]`
Initial public release (FW 0.64) 2016-02-22 23:03:50 +00:00			`set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]`
			`set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]`