misc tool updates

2025-02-05 12:33:24 +00:00 · 2020-04-28 18:48:35 +03:00 · 2020-04-28 18:48:35 +03:00 · 2319a6f8bd
commit 2319a6f8bd
parent 4dab90a651
16 changed files with 64 additions and 54 deletions
--- a/ossc_rtl.project
+++ b/ossc_rtl.project
@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_rtl" InternalType="">
+<CodeLite_Project Name="ossc_rtl" InternalType="" Version="11000">
  <VirtualDirectory Name="ip">
    <VirtualDirectory Name="nios2_hw_crc">
      <VirtualDirectory Name="hdl">
@ -24,6 +24,23 @@
  </VirtualDirectory>
  <Description/>
  <Dependencies/>
+  <VirtualDirectory Name="rtl">
+    <File Name="rtl/ir_rcv.v"/>
+    <File Name="rtl/ossc.v"/>
+    <File Name="rtl/pll_2x.v"/>
+    <File Name="rtl/pll_3x_lowfreq.v"/>
+    <File Name="rtl/pll_3x_lowfreq_bb.v"/>
+    <File Name="rtl/linebuf_inst.v"/>
+    <File Name="rtl/videogen.v"/>
+    <File Name="rtl/timescale.v"/>
+    <File Name="rtl/pll_2x_bb.v"/>
+    <File Name="rtl/linebuf.v"/>
+    <File Name="rtl/pll_3x.v"/>
+    <File Name="rtl/scanconverter.v"/>
+    <File Name="rtl/linebuf_bb.v"/>
+  </VirtualDirectory>
+  <Dependencies Name="Debug"/>
+  <Dependencies Name="Release"/>
  <Settings Type="Dynamic Library">
    <GlobalSettings>
      <Compiler Options="" C_Options="" Assembler="">
@ -41,6 +58,7 @@
      <Linker Options="" Required="yes"/>
      <ResourceCompiler Options="" Required="no"/>
      <General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
      <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
        <![CDATA[]]>
      </Environment>
@ -79,6 +97,7 @@
      <Linker Options="-O2" Required="yes"/>
      <ResourceCompiler Options="" Required="no"/>
      <General OutputFile="" IntermediateDirectory="./Release" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
      <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
        <![CDATA[]]>
      </Environment>
@ -111,21 +130,4 @@
      </Completion>
    </Configuration>
  </Settings>
-  <VirtualDirectory Name="rtl">
-    <File Name="rtl/ir_rcv.v"/>
-    <File Name="rtl/ossc.v"/>
-    <File Name="rtl/pll_2x.v"/>
-    <File Name="rtl/pll_3x_lowfreq.v"/>
-    <File Name="rtl/pll_3x_lowfreq_bb.v"/>
-    <File Name="rtl/linebuf_inst.v"/>
-    <File Name="rtl/videogen.v"/>
-    <File Name="rtl/timescale.v"/>
-    <File Name="rtl/pll_2x_bb.v"/>
-    <File Name="rtl/linebuf.v"/>
-    <File Name="rtl/pll_3x.v"/>
-    <File Name="rtl/scanconverter.v"/>
-    <File Name="rtl/linebuf_bb.v"/>
-  </VirtualDirectory>
-  <Dependencies Name="Debug"/>
-  <Dependencies Name="Release"/>
 </CodeLite_Project>
--- a/ossc_sw_bsp.project
+++ b/ossc_sw_bsp.project
@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_sw_bsp" InternalType="" Version="10.0.0">
+<CodeLite_Project Name="ossc_sw_bsp" InternalType="" Version="11000">
  <Plugins>
    <Plugin Name="qmake">
      <![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
--- a/rtl/char_array.qip
+++ b/rtl/char_array.qip
@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]
--- a/rtl/char_array.v
+++ b/rtl/char_array.v
@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 // ************************************************************


-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.


 // synopsys translate_off
--- a/rtl/char_rom.qip
+++ b/rtl/char_rom.qip
@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]
--- a/rtl/char_rom.v
+++ b/rtl/char_rom.v
@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 // ************************************************************


-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.


 // synopsys translate_off
--- a/rtl/linebuf.qip
+++ b/rtl/linebuf.qip
@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]
--- a/rtl/linebuf.v
+++ b/rtl/linebuf.v
@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 // ************************************************************


-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.


 // synopsys translate_off
--- a/rtl/lpm_mult_4_hybr_ref.qip
+++ b/rtl/lpm_mult_4_hybr_ref.qip
@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_bb.v"]
--- a/rtl/lpm_mult_4_hybr_ref.v
+++ b/rtl/lpm_mult_4_hybr_ref.v
@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 // ************************************************************


-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.


 // synopsys translate_off
--- a/rtl/lpm_mult_4_hybr_ref_pre.qip
+++ b/rtl/lpm_mult_4_hybr_ref_pre.qip
@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre_bb.v"]
--- a/rtl/lpm_mult_4_hybr_ref_pre.v
+++ b/rtl/lpm_mult_4_hybr_ref_pre.v
@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 // ************************************************************


-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.


 // synopsys translate_off
--- a/rtl/lpm_mult_4_sl.qip
+++ b/rtl/lpm_mult_4_sl.qip
@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "19.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl_bb.v"]
--- a/rtl/lpm_mult_4_sl.v
+++ b/rtl/lpm_mult_4_sl.v
@ -14,13 +14,13 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
+// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 // ************************************************************


-//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Copyright (C) 2019  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
+//and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
 //(including device programming or simulation files), and any 
 //associated documentation or information are expressly subject 
@ -30,7 +30,8 @@
 //agreement, including, without limitation, that your use is for
 //the sole purpose of programming logic devices manufactured by
 //Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details.
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.


 // synopsys translate_off
--- a/software/ossc_sw.project
+++ b/software/ossc_sw.project
@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="ossc_sw" InternalType="" Version="10.0.0">
+<CodeLite_Project Name="ossc_sw" InternalType="" Version="11000">
  <Plugins>
    <Plugin Name="qmake">
      <![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
--- a/tools.project
+++ b/tools.project
@ -1,6 +1,9 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<CodeLite_Project Name="tools" InternalType="">
+<CodeLite_Project Name="tools" InternalType="" Version="11000">
  <Plugins>
+    <Plugin Name="qmake">
+      <![CDATA[00010001N0007Release000000000000]]>
+    </Plugin>
    <Plugin Name="CMakePlugin">
      <![CDATA[[{
  "name": "Release",
@ -13,9 +16,6 @@
  "parentProject": ""
 }]]]>
    </Plugin>
-    <Plugin Name="qmake">
-      <![CDATA[00010001N0007Release000000000000]]>
-    </Plugin>
  </Plugins>
  <Description/>
  <Dependencies/>
@ -39,6 +39,7 @@
      <Linker Options="" Required="yes"/>
      <ResourceCompiler Options="" Required="no"/>
      <General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
      <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
        <![CDATA[]]>
      </Environment>
@ -77,6 +78,7 @@
      <Linker Options="-O2" Required="yes"/>
      <ResourceCompiler Options="" Required="no"/>
      <General OutputFile="$(IntermediateDirectory)/fw2" IntermediateDirectory="tools" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
+      <BuildSystem Name="Default"/>
      <Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
        <![CDATA[]]>
      </Environment>