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Improve lo-res mode processing features

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* workaround for phase shift issue on optimized modes
* add hscale option for 256x240 opt Line3x mode
* distribute video modes to groups and allow passthru for all modes
This commit is contained in:
marqs
2017-01-23 00:56:17 +02:00
parent a03c01ca4d
commit 434186d64e
19 changed files with 2485 additions and 1440 deletions
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software/sys_controller_bsp/libhal_bsp.a
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software/sys_controller_bsp/settings.bsp
+21 -15
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@@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Jan 7, 2017 11:01:41 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1483822901087</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Jan 23, 2017 12:33:30 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1485124410921</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
@@ -910,20 +910,20 @@
<addressSpan>40960</addressSpan>
<attributes>memory</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>i2c_opencores_1</slaveDescriptor>
<addressRange>0x00821000 - 0x0082101F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>timer_0</slaveDescriptor>
<addressRange>0x00821020 - 0x0082103F</addressRange>
<addressRange>0x00821000 - 0x0082101F</addressRange>
<addressSpan>32</addressSpan>
<attributes>timer</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>epcq_controller_0_avl_csr</slaveDescriptor>
<addressRange>0x00821020 - 0x0082103F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>i2c_opencores_1</slaveDescriptor>
<addressRange>0x00821040 - 0x0082105F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
@@ -935,38 +935,44 @@
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_4</slaveDescriptor>
<slaveDescriptor>pio_5</slaveDescriptor>
<addressRange>0x00821080 - 0x0082108F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_3</slaveDescriptor>
<slaveDescriptor>pio_4</slaveDescriptor>
<addressRange>0x00821090 - 0x0082109F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_2</slaveDescriptor>
<slaveDescriptor>pio_3</slaveDescriptor>
<addressRange>0x008210A0 - 0x008210AF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_1</slaveDescriptor>
<slaveDescriptor>pio_2</slaveDescriptor>
<addressRange>0x008210B0 - 0x008210BF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_0</slaveDescriptor>
<slaveDescriptor>pio_1</slaveDescriptor>
<addressRange>0x008210C0 - 0x008210CF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_0</slaveDescriptor>
<addressRange>0x008210D0 - 0x008210DF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
<addressRange>0x008210D0 - 0x008210D7</addressRange>
<addressRange>0x008210E0 - 0x008210E7</addressRange>
<addressSpan>8</addressSpan>
<attributes>printable</attributes>
</MemoryMap>
software/sys_controller_bsp/system.h
+40 -13
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@@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sat Dec 31 11:45:57 EET 2016
* Generated: Sat Jan 21 12:40:58 EET 2017
*/
/*
@@ -175,19 +175,19 @@
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x8210d0
#define ALT_STDERR_BASE 0x8210e0
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x8210d0
#define ALT_STDIN_BASE 0x8210e0
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x8210d0
#define ALT_STDOUT_BASE 0x8210e0
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
@@ -201,7 +201,7 @@
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821040
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821020
#define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS64"
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
@@ -265,7 +265,7 @@
*/
#define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores
#define I2C_OPENCORES_1_BASE 0x821000
#define I2C_OPENCORES_1_BASE 0x821040
#define I2C_OPENCORES_1_IRQ 4
#define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1"
@@ -279,7 +279,7 @@
*/
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x8210d0
#define JTAG_UART_0_BASE 0x8210e0
#define JTAG_UART_0_IRQ 1
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
@@ -326,7 +326,7 @@
*/
#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
#define PIO_0_BASE 0x8210c0
#define PIO_0_BASE 0x8210d0
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_0_CAPTURE 0
@@ -353,7 +353,7 @@
*/
#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
#define PIO_1_BASE 0x8210b0
#define PIO_1_BASE 0x8210c0
#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_1_CAPTURE 0
@@ -380,7 +380,7 @@
*/
#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
#define PIO_2_BASE 0x8210a0
#define PIO_2_BASE 0x8210b0
#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_2_CAPTURE 0
@@ -407,7 +407,7 @@
*/
#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
#define PIO_3_BASE 0x821090
#define PIO_3_BASE 0x8210a0
#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_3_CAPTURE 0
@@ -434,7 +434,7 @@
*/
#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
#define PIO_4_BASE 0x821080
#define PIO_4_BASE 0x821090
#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_4_CAPTURE 0
@@ -455,6 +455,33 @@
#define PIO_4_TYPE "altera_avalon_pio"
/*
* pio_5 configuration
*
*/
#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
#define PIO_5_BASE 0x821080
#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_5_CAPTURE 0
#define PIO_5_DATA_WIDTH 32
#define PIO_5_DO_TEST_BENCH_WIRING 0
#define PIO_5_DRIVEN_SIM_VALUE 0
#define PIO_5_EDGE_TYPE "NONE"
#define PIO_5_FREQ 27000000
#define PIO_5_HAS_IN 0
#define PIO_5_HAS_OUT 1
#define PIO_5_HAS_TRI 0
#define PIO_5_IRQ -1
#define PIO_5_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PIO_5_IRQ_TYPE "NONE"
#define PIO_5_NAME "/dev/pio_5"
#define PIO_5_RESET_VALUE 0
#define PIO_5_SPAN 16
#define PIO_5_TYPE "altera_avalon_pio"
/*
* timer_0 configuration
*
@@ -462,7 +489,7 @@
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x821020
#define TIMER_0_BASE 0x821000
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 27000000