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* Fix scanline rendering issues 

* Add initial input and SDTV sync glitch filter settings
* Modify input initialization logic
* Fix debug build warnings
This commit is contained in:
marqs 2016-08-14 18:57:50 +03:00
parent c8b542b917
commit a488422089
16 changed files with 912 additions and 870 deletions
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42
rtl/scanconverter.v
View File

@ -92,7 +92,7 @@ reg VSYNC_1x, VSYNC_2x, VSYNC_pp1;
reg [11:0] HSYNC_start;
reg FID_prev;
reg FID_1x, FID_prev;
wire DATA_enable_act;
reg DATA_enable_pp1;
@ -120,6 +120,7 @@ reg h_enable_3x, h_enable_3x_h1x, v_enable_3x, v_enable_3x_h1x;
reg prev_hs, prev_vs;
reg [11:0] hmax[0:1];
reg line_idx;
reg [1:0] line_out_idx_2x, line_out_idx_3x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x, warn_pll_lock_lost_3x_lowfreq;
@ -166,7 +167,7 @@ function [8:0] apply_scanlines;
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else if ((mode == `SCANLINES_V) & (actid == pixid))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else if ((mode == `SCANLINES_ALT) & ((actid[0]^fid) == lineid[0]))
else if ((mode == `SCANLINES_ALT) & ({actid[1], actid[0]^fid} == lineid))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else
apply_scanlines = data;
@ -236,7 +237,7 @@ begin
linebuf_rdclock = pclk_2x;
linebuf_hoffset = hcnt_2x;
pclk_act = pclk_2x;
slid_act = {1'b0, vcnt_2x[0]};
slid_act = {line_out_idx_2x[1], line_out_idx_2x[0]^FID_1x};
hcnt_act = hcnt_2x;
vcnt_act = vcnt_2x>>1;
end
@ -245,6 +246,7 @@ begin
G_act = G_lbuf;
B_act = B_lbuf;
VSYNC_act = VSYNC_1x;
slid_act = line_out_idx_3x;
case (H_L3MODE)
`LINETRIPLE_M0: begin
DATA_enable_act = (h_enable_3x & v_enable_3x);
@ -256,7 +258,6 @@ begin
pclk_act = pclk_3x;
hcnt_act = hcnt_3x;
vcnt_act = vcnt_3x/2'h3; //divider generated
slid_act = (vcnt_3x % 2'h3);
end
`LINETRIPLE_M1: begin
DATA_enable_act = (h_enable_3x & v_enable_3x);
@ -268,7 +269,6 @@ begin
pclk_act = pclk_4x;
hcnt_act = hcnt_4x;
vcnt_act = vcnt_3x/2'h3; //divider generated
slid_act = (vcnt_3x % 2'h3);
end
`LINETRIPLE_M2: begin
DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x);
@ -280,7 +280,6 @@ begin
pclk_act = pclk_3x_h4x;
hcnt_act = hcnt_3x_h4x;
vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
slid_act = (vcnt_3x_h1x % 2'h3);
end
`LINETRIPLE_M3: begin
DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x);
@ -292,7 +291,6 @@ begin
pclk_act = pclk_3x_h5x;
hcnt_act = hcnt_3x_h5x;
vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
slid_act = (vcnt_3x_h1x % 2'h3);
end
endcase
end
@ -377,9 +375,9 @@ begin
VSYNC_pp1 <= VSYNC_act;
DATA_enable_pp1 <= DATA_enable_act;
R_out <= apply_scanlines(V_SCANLINES, R_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_prev);
G_out <= apply_scanlines(V_SCANLINES, G_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_prev);
B_out <= apply_scanlines(V_SCANLINES, B_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_prev);
R_out <= apply_scanlines(V_SCANLINES, R_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
G_out <= apply_scanlines(V_SCANLINES, G_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
B_out <= apply_scanlines(V_SCANLINES, B_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
HSYNC_out <= HSYNC_pp1;
VSYNC_out <= VSYNC_pp1;
DATA_enable <= DATA_enable_pp1;
@ -458,6 +456,7 @@ begin
VSYNC_1x <= 0;
h_enable_1x <= 0;
v_enable_1x <= 0;
FID_1x <= 0;
end
else
begin
@ -468,6 +467,7 @@ begin
line_idx <= line_idx ^ 1'b1;
vcnt_1x <= vcnt_1x + 1'b1;
vcnt_1x_tvp <= vcnt_1x_tvp + 1'b1;
FID_1x <= fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] ? 0 : (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] ? (vcnt_1x > (V_BACKPORCH + V_ACTIVE)) : FID_in);
end
else
begin
@ -542,13 +542,20 @@ begin
VSYNC_2x <= 0;
h_enable_2x <= 0;
v_enable_2x <= 0;
line_out_idx_2x <= 0;
end
else
begin
if ((pclk_1x == 1'b0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
hcnt_2x <= 0;
begin
hcnt_2x <= 0;
line_out_idx_2x <= 0;
end
else if (hcnt_2x == hmax[~line_idx]) //line_idx_prev?
hcnt_2x <= 0;
begin
hcnt_2x <= 0;
line_out_idx_2x <= line_out_idx_2x + 1'b1;
end
else
hcnt_2x <= hcnt_2x + 1'b1;
@ -599,13 +606,20 @@ begin
v_enable_3x <= 0;
pclk_3x_cnt <= 0;
pclk_1x_prev3x <= 0;
line_out_idx_3x <= 0;
end
else
begin
if ((pclk_3x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
hcnt_3x <= 0;
begin
hcnt_3x <= 0;
line_out_idx_3x <= 0;
end
else if (hcnt_3x == hmax[~line_idx]) //line_idx_prev?
hcnt_3x <= 0;
begin
hcnt_3x <= 0;
line_out_idx_3x <= line_out_idx_3x + 1'b1;
end
else
hcnt_3x <= hcnt_3x + 1'b1;

2
software/sys_controller/it6613/it6613.c
View File

@ -55,7 +55,7 @@ int init_it() {
vendor_id = read_it(IT_VENDORID);
device_id = read_it(IT_DEVICEID);
printf("VEN: 0x%.2X, DEV: 0x%.2X\n", vendor_id, device_id);
printf("VEN: 0x%.2lX, DEV: 0x%.2lX\n", vendor_id, device_id);
if (!((vendor_id == IT6613_VENDORID) && (device_id == IT6613_DEVICEID)))
return -1;

2
software/sys_controller/it6613/it6613_drv.c
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@ -2075,7 +2075,7 @@ ReadEDID(BYTE *pData,BYTE bSegment,BYTE offset,SHORT Count)
if(TimeOut == 0)
{
ErrorF("ReadEDID(): DDC TimeOut. \n",ucdata) ;
ErrorF("ReadEDID(): DDC TimeOut (DDC_STATUS = %02X). \n",ucdata) ;
return ER_FAIL ;
}

1610
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

50
software/sys_controller/ossc/av_controller.c
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@ -40,11 +40,11 @@
#include "HDMI_TX.h"
#include "hdmitx.h"
#define LINECNT_THOLD 1
#define STABLE_THOLD 1
#define MIN_LINES_PROGRESSIVE 200
#define MIN_LINES_INTERLACED 400
#define SYNC_LOSS_THOLD 5
#define SYNC_LOCK_THOLD 3
#define SYNC_LOSS_THOLD -5
#define STATUS_TIMEOUT 10000
// Current mode
@ -97,7 +97,7 @@ void set_lpf(alt_u8 lpf)
{
alt_u32 pclk;
pclk = (clkrate[REFCLK_EXT27]/cm.clkcnt)*video_modes[cm.id].h_total;
printf("PCLK: %uHz\n", pclk);
printf("PCLK: %luHz\n", pclk);
//Auto
if (lpf == 0) {
@ -146,7 +146,7 @@ status_t get_status(tvp_input_t input, video_format format)
alt_u8 vsyncmode;
alt_u16 fpga_totlines;
status_t status;
static alt_u8 act_ctr;
static alt_8 act_ctr;
alt_u32 ctr;
int valid_linecnt;
@ -161,7 +161,7 @@ status_t get_status(tvp_input_t input, video_format format)
}
sync_active = tvp_check_sync(input, format);
vsyncmode = IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16;
vsyncmode = cm.sync_active ? (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) : 0;
data1 = tvp_readreg(TVP_LINECNT1);
data2 = tvp_readreg(TVP_LINECNT2);
@ -184,18 +184,23 @@ status_t get_status(tvp_input_t input, video_format format)
// TVP7002 may randomly report "no sync" (especially with arcade boards),
// thus disable output only after N consecutive "no sync"-events
if (!cm.sync_active && sync_active && valid_linecnt) {
cm.sync_active = sync_active;
status = ACTIVITY_CHANGE;
act_ctr = 0;
} else if (cm.sync_active && (!sync_active || !valid_linecnt)) {
printf("Sync down in %u...\n", SYNC_LOSS_THOLD-act_ctr);
if (act_ctr >= SYNC_LOSS_THOLD) {
printf("Sync up in %d...\n", SYNC_LOCK_THOLD-act_ctr);
if (act_ctr >= SYNC_LOCK_THOLD) {
act_ctr = 0;
cm.sync_active = sync_active;
cm.sync_active = 1;
status = ACTIVITY_CHANGE;
} else {
act_ctr++;
}
} else if (cm.sync_active && (!sync_active || !valid_linecnt)) {
printf("Sync down in %d...\n", act_ctr-SYNC_LOSS_THOLD);
if (act_ctr <= SYNC_LOSS_THOLD) {
act_ctr = 0;
cm.sync_active = 0;
status = ACTIVITY_CHANGE;
} else {
act_ctr--;
}
} else {
act_ctr = 0;
}
@ -205,8 +210,10 @@ status_t get_status(tvp_input_t input, video_format format)
clkcnt = ((data2 & 0x0f) << 8) | data1;
if (valid_linecnt) {
if ((abs((alt_16)totlines - (alt_16)cm.totlines) > LINECNT_THOLD) || (clkcnt != cm.clkcnt) || (progressive != cm.progressive)) {
printf("totlines: %u (cur) / %u (prev), clkcnt: %u (cur) / %u (prev). Data1: 0x%.2x, Data2: 0x%.2x\n", (unsigned)totlines, (unsigned)cm.totlines, (unsigned)clkcnt, (unsigned)cm.clkcnt, (unsigned)data1, (unsigned)data2);
if ((totlines != cm.totlines) || (clkcnt != cm.clkcnt) || (progressive != cm.progressive)) {
printf("totlines: %lu (cur) / %lu (prev), clkcnt: %lu (cur) / %lu (prev). Data1: 0x%.2x, Data2: 0x%.2x\n", totlines, cm.totlines, clkcnt, cm.clkcnt, (unsigned)data1, (unsigned)data2);
/*if (!cm.sync_active)
act_ctr = 0;*/
stable_frames = 0;
} else if (stable_frames != STABLE_THOLD) {
stable_frames++;
@ -244,6 +251,9 @@ status_t get_status(tvp_input_t input, video_format format)
if (tc.vsync_thold != cm.cc.vsync_thold)
tvp_set_ssthold(tc.vsync_thold);
if (tc.sd_sync_win != cm.cc.sd_sync_win)
tvp_setup_glitchstripper(target_type, tc.sd_sync_win);
if ((tc.pre_coast != cm.cc.pre_coast) || (tc.post_coast != cm.cc.post_coast))
tvp_set_hpllcoast(tc.pre_coast, tc.post_coast);
@ -325,7 +335,7 @@ void program_mode()
if ((cm.clkcnt != 0) && (cm.totlines != 0)) { //prevent div by 0
h_hz = clkrate[REFCLK_EXT27]/cm.clkcnt;
v_hz_x100 = cm.progressive ? (100*clkrate[REFCLK_EXT27]/cm.clkcnt)/cm.totlines : (2*(100*clkrate[REFCLK_EXT27]/cm.clkcnt))/cm.totlines;
v_hz_x100 = cm.progressive ? ((100*clkrate[REFCLK_EXT27])/cm.totlines)/cm.clkcnt : (2*((100*clkrate[REFCLK_EXT27])/cm.totlines))/cm.clkcnt;
} else {
h_hz = 15700;
v_hz_x100 = 6000;
@ -340,15 +350,13 @@ void program_mode()
sniprintf(row1, LCD_ROW_LEN+1, "%s %u%c", avinput_str[cm.avinput], (unsigned)cm.totlines, cm.progressive ? 'p' : 'i');
sniprintf(row2, LCD_ROW_LEN+1, "%u.%.2ukHz %u.%.2uHz", (unsigned)(h_hz/1000), (unsigned)((h_hz%1000)/10), (unsigned)(v_hz_x100/100), (unsigned)(v_hz_x100%100));
//strncpy(row1, avinput_str[cm.avinput], LCD_ROW_LEN+1);
//strncpy(row2, avinput_str[cm.avinput], LCD_ROW_LEN+1);
if (!menu_active)
lcd_write_status();
//printf ("Get mode id with %u %u %f\n", totlines, progressive, hz);
cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, target_typemask, cm.cc.linemult_target, cm.cc.l3_mode, cm.cc.s480p_mode);
if ( cm.id == -1) {
if (cm.id == -1) {
printf ("Error: no suitable mode found, defaulting to 240p\n");
cm.id = 4;
}
@ -357,7 +365,7 @@ void program_mode()
printf("Mode %s selected\n", video_modes[cm.id].name);
tvp_source_setup(cm.id, target_type, cm.cc.en_alc, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold);
tvp_source_setup(cm.id, target_type, cm.cc.en_alc, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold, cm.cc.sd_sync_win);
set_lpf(cm.cc.video_lpf);
set_videoinfo();
}
@ -475,6 +483,8 @@ int main()
while (1) {}
}
target_mode = tc.def_input;
// Mainloop
while(1) {
// Read remote control and PCB button status
@ -482,7 +492,6 @@ int main()
remote_code = input_vec & RC_MASK;
btn_code = ~input_vec & PB_MASK;
remote_rpt = input_vec >> 24;
target_mode = AV_KEEP;
if ((remote_rpt == 0) || ((remote_rpt > 1) && (remote_rpt < 6)) || (remote_rpt == remote_rpt_prev))
remote_code = 0;
@ -615,6 +624,7 @@ int main()
btn_code_prev = btn_code;
remote_rpt_prev = remote_rpt;
target_mode = AV_KEEP;
usleep(300); // Avoid executing mainloop multiple times per vsync
}

2
software/sys_controller/ossc/av_controller.h
View File

@ -24,7 +24,7 @@
#define HDMITX_MODE_MASK 0x00040000
static const char *avinput_str[] = { "-", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr" };
static const char *avinput_str[] = { "Test pattern", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr" };
typedef enum {
AV_KEEP = 0,

1
software/sys_controller/ossc/avconfig.c
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@ -37,6 +37,7 @@ const avconfig_t tc_default = {
.sampler_phase = DEFAULT_SAMPLER_PHASE,
.sync_vth = DEFAULT_SYNC_VTH,
.vsync_thold = DEFAULT_VSYNC_THOLD,
.sd_sync_win = DEFAULT_SD_SYNC_WIN,
.en_alc = 1,
.pre_coast = DEFAULT_PRE_COAST,
.post_coast = DEFAULT_POST_COAST,

3
software/sys_controller/ossc/avconfig.h
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@ -29,6 +29,7 @@
#define SYNC_VTH_MAX 31
#define VSYNC_THOLD_MIN 10
#define VSYNC_THOLD_MAX 200
#define SD_SYNC_WIN_MAX 255
#define PLL_COAST_MAX 5
#define SL_MODE_MAX 2
@ -50,6 +51,7 @@ typedef struct {
alt_u8 ypbpr_cs;
alt_u8 sync_vth;
alt_u8 vsync_thold;
alt_u8 sd_sync_win;
alt_u8 sync_lpf;
alt_u8 video_lpf;
alt_u8 en_alc;
@ -57,6 +59,7 @@ typedef struct {
alt_u8 post_coast;
alt_u8 edtv_l2x;
alt_u8 interlace_pt;
alt_u8 def_input;
} __attribute__((packed)) avconfig_t;
int set_default_avconfig();

4
software/sys_controller/ossc/controls.c
View File

@ -89,10 +89,10 @@ void parse_control()
int i;
if (remote_code)
printf("RCODE: 0x%.4x, %u\n", remote_code, remote_rpt);
printf("RCODE: 0x%.4lx, %d\n", remote_code, remote_rpt);
if (btn_code_prev == 0 && btn_code != 0)
printf("BCODE: 0x%.2x\n", btn_code>>16);
printf("BCODE: 0x%.2lx\n", btn_code>>16);
for (i = RC_BTN1; i < REMOTE_MAX_KEYS; i++) {
if (remote_code == rc_keymap[i])

2
software/sys_controller/ossc/firmware.h
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@ -23,7 +23,7 @@
#include "alt_types.h"
#define FW_VER_MAJOR 0
#define FW_VER_MINOR 71
#define FW_VER_MINOR 72
#define FW_UPDATE_RETRIES 3

11
software/sys_controller/ossc/menu.c
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@ -39,17 +39,18 @@ alt_u8 menu_active;
static const char *off_on_desc[] = { "Off", "On" };
static const char *video_lpf_desc[] = { "Auto", "Off", "95MHz (HDTV II)", "35MHz (HDTV I)", "16MHz (EDTV)", "9MHz (SDTV)" };
static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709" };
static const char *s480p_mode_desc[] = { "Auto", "DTV 480p", "VGA 640x480" };
static const char *s480p_mode_desc[] = { "Auto", "DTV 480p", "VESA 640x480@60" };
static const char *sync_lpf_desc[] = { "Off", "33MHz (min)", "10MHz (med)", "2.5MHz (max)" };
static const char *l3_mode_desc[] = { "Generic 16:9", "Generic 4:3", "320x240 optim.", "256x240 optim." };
static const char *tx_mode_desc[] = { "HDMI", "DVI" };
static const char *sl_mode_desc[] = { "Off", "Auto", "Manual" };
static const char *sl_type_desc[] = { "Horizontal", "Vertical", "Alternating" };
static const char *sl_id_desc[] = { "Even", "Odd" };
static const char *sl_id_desc[] = { "Top", "Bottom" };
static void sampler_phase_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d deg", (v*1125)/100); }
static void sync_vth_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", (v*1127)/100); }
static void vsync_thold_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%u us", (unsigned)(((1000000U*v)/(clkrate[REFCLK_INTCLK]/1000))/1000), (unsigned)((((1000000U*v)/(clkrate[REFCLK_INTCLK]/1000))%1000)/100)); }
static void intclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(clkrate[REFCLK_INTCLK]/1000))/1000), (unsigned)((((1000000U*v)/(clkrate[REFCLK_INTCLK]/1000))%1000)/10)); }
static void extclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(clkrate[REFCLK_EXT27]/1000))/1000), (unsigned)((((1000000U*v)/(clkrate[REFCLK_EXT27]/1000))%1000)/10)); }
static void sl_str_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u%%", ((v+1)*625)/100); }
static void lines_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u lines", v); }
static void pixels_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u pixels", v); }
@ -69,7 +70,8 @@ MENU(menu_sampling, P99_PROTECT({ \
MENU(menu_sync, P99_PROTECT({ \
{ "Analog sync LPF", OPT_AVCONFIG_SELECTION, { .sel = { &tc.sync_lpf, OPT_WRAP, SETTING_ITEM(sync_lpf_desc) } } },
{ "Analog sync Vth", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sync_vth, OPT_NOWRAP, 0, SYNC_VTH_MAX, sync_vth_disp } } },
{ "Vsync threshold", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.vsync_thold, OPT_NOWRAP, VSYNC_THOLD_MIN, VSYNC_THOLD_MAX, vsync_thold_disp } } },
{ "Vsync threshold", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.vsync_thold, OPT_NOWRAP, VSYNC_THOLD_MIN, VSYNC_THOLD_MAX, intclks_to_time_disp } } },
{ "GlitchFilter len", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sd_sync_win, OPT_NOWRAP, 0, SD_SYNC_WIN_MAX, extclks_to_time_disp } } },
{ "H-PLL Pre-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.pre_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
{ "H-PLL Post-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.post_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
}))
@ -80,6 +82,7 @@ MENU(menu_output, P99_PROTECT({ \
{ "480p/576p lineX2", OPT_AVCONFIG_SELECTION, { .sel = { &tc.edtv_l2x, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
{ "480i/576i passtr", OPT_AVCONFIG_SELECTION, { .sel = { &tc.interlace_pt, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
{ "TX mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } },
{ "Initial input", OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } },
}))
MENU(menu_postproc, P99_PROTECT({ \

1
software/sys_controller/ossc/sysconfig.h
View File

@ -25,6 +25,7 @@
#define ErrorF(...)
#define printf(...)
#else
#include <stdio.h>
#define OS_PRINTF printf
#define ErrorF printf
// use reduced printf

37
software/sys_controller/tvp7002/tvp7002.c
View File

@ -205,7 +205,7 @@ void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 pll
pclk_est = ((alt_u32)h_samplerate * v_lines * hz) / 1000; //in kHz
printf("Estimated PCLK: %u.%.3u MHz\n", pclk_est/1000, pclk_est%1000);
printf("Estimated PCLK: %lu.%.3lu MHz\n", pclk_est/1000, pclk_est%1000);
if (pclk_est < 36000) {
vco_range = 0;
@ -319,20 +319,13 @@ void tvp_set_alc(alt_u8 en_alc, video_type type)
}
}
void tvp_source_setup(alt_8 modeid, video_type type, alt_u8 en_alc, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold)
void tvp_setup_glitchstripper(video_type type, alt_u8 sd_winwidth)
{
// Clamp position and ALC
tvp_set_clamp_position(type);
tvp_set_alc(en_alc, type);
tvp_set_ssthold(vsync_thold);
// Macrovision enable/disable, coast disable for RGBHV.
// Coast needs to be enabled when HSYNC is missing during VSYNC. Valid only for RGBHV?
// Macrovision should be enabled when serration pulses etc. present, so disable only for RGBHV.
// Setup Macrovision stripper and H-PLL coast.
// Coast needs to be enabled when HSYNC is missing during VSYNC. Disabled only for RGBHV.
// Macrovision stripper filters out glitches and serration pulses that may occur outside of sync window (HSYNC_lead +- TVP_MVSWIDTH*37ns). Enabled for all inputs.
switch (type) {
case VIDEO_PC:
//tvp_writereg(TVP_MISCCTRL4, 0x04);
tvp_writereg(TVP_MISCCTRL4, 0x0C);
tvp_writereg(TVP_MVSWIDTH, 0x03);
break;
@ -340,15 +333,29 @@ void tvp_source_setup(alt_8 modeid, video_type type, alt_u8 en_alc, alt_u32 vlin
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x0E);
break;
case VIDEO_LDTV:
case VIDEO_SDTV:
case VIDEO_EDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x88); // TODO: check mode
tvp_writereg(TVP_MVSWIDTH, 0x44);
break;
case VIDEO_LDTV:
case VIDEO_SDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, sd_winwidth);
break;
default:
break;
}
}
void tvp_source_setup(alt_8 modeid, video_type type, alt_u8 en_alc, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sd_sync_win)
{
// Clamp position and ALC
tvp_set_clamp_position(type);
tvp_set_alc(en_alc, type);
tvp_set_ssthold(vsync_thold);
tvp_setup_glitchstripper(type, sd_sync_win);
tvp_setup_hpll(video_modes[modeid].h_total, vlines, hz, !!(video_modes[modeid].flags & MODE_PLLDIVBY2));

5
software/sys_controller/tvp7002/tvp7002.h
View File

@ -28,6 +28,7 @@
#define I2CA_BASE I2C_OPENCORES_0_BASE
#define DEFAULT_VSYNC_THOLD 0x44
#define DEFAULT_SD_SYNC_WIN 0x88
typedef enum {
TVP_INPUT1 = 0,
@ -91,7 +92,9 @@ void tvp_set_sog_thold(alt_u8 val);
void tvp_set_alc(alt_u8 en_alc, video_type type);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u8 en_alc, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold);
void tvp_setup_glitchstripper(video_type type, alt_u8 sd_winwidth);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u8 en_alc, alt_u32 vlines, alt_u8 hz, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sd_sync_win);
void tvp_source_sel(tvp_input_t input, video_format fmt);

6
software/sys_controller_bsp/settings.bsp
View File

@ -2,9 +2,9 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Jul 5, 2016 9:45:39 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1467744339754</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspGeneratedTimeStamp>Aug 11, 2016 10:54:37 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1470945277261</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>/home/markus/Code/ossc/software/sys_controller_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 15.1 185 (Future versions may contain additional information.) -->
<!-- 2016.07.05.21:14:28 -->
<!-- 2016.08.11.01:11:42 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1467742468</value>
<value>1470867102</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>