mirror of https://github.com/marqs85/ossc.git
Add reverse LPF feature
reverse LPF can be used to mostly reverse the blur on pre 1-CHIP SNES. For best results use 256x240 optimized mode.
This commit is contained in:
paulb-nl
parent
9d14cc776e
commit
ac16008076
1
ossc.qsf
1
ossc.qsf
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@ -238,4 +238,5 @@ set_global_assignment -name QIP_FILE rtl/pll_2x.qip
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set_global_assignment -name QIP_FILE rtl/pll_3x.qip
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name SEED 27
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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7
ossc.sdc
7
ossc.sdc
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@ -61,7 +61,7 @@ set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv pclk_2x pcl
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set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_4x}]
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# Ignore paths which would result from pclk_act switchover during postprocess chain
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set pclk_act_regs [get_cells {scanconverter:scanconverter_inst|R_out* \
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set pclk_act_regs [get_registers {scanconverter:scanconverter_inst|R_out* \
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scanconverter:scanconverter_inst|G_out* \
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scanconverter:scanconverter_inst|B_out* \
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scanconverter:scanconverter_inst|HSYNC_out* \
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@ -69,7 +69,10 @@ set pclk_act_regs [get_cells {scanconverter:scanconverter_inst|R_out* \
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scanconverter:scanconverter_inst|DE_out* \
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scanconverter:scanconverter_inst|*_pp1* \
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scanconverter:scanconverter_inst|*_pp2* \
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scanconverter:scanconverter_inst|*_pp3*}]
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scanconverter:scanconverter_inst|*_pp3* \
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scanconverter:scanconverter_inst|*_pp4* \
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scanconverter:scanconverter_inst|*_pp5* \
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scanconverter:scanconverter_inst|*_pp6*}]
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set_false_path -from [get_clocks {pclk_sdtv}] -to $pclk_act_regs
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set_false_path -from [get_clocks {pclk_sdtv}] -to [get_ports HDMI_TX_*]
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@ -92,14 +92,17 @@ wire linebuf_rdclock;
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//RGB signals®isters: 8 bits per component -> 16.7M colors
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wire [7:0] R_act, G_act, B_act;
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wire [7:0] R_lbuf, G_lbuf, B_lbuf;
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reg [7:0] R_in_L, G_in_L, B_in_L, R_in_LL, G_in_LL, B_in_LL, R_1x, G_1x, B_1x, R_pp3, G_pp3, B_pp3;
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reg [7:0] R_in_L, G_in_L, B_in_L, R_in_LL, G_in_LL, B_in_LL, R_1x, G_1x, B_1x;
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reg [7:0] R_pp3, G_pp3, B_pp3, R_pp4, G_pp4, B_pp4, R_pp5, G_pp5, B_pp5, R_pp6, G_pp6, B_pp6;
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reg [7:0] R_prev_pp2, G_prev_pp2, B_prev_pp2, R_prev_pp3, G_prev_pp3, B_prev_pp3, R_prev_pp4, G_prev_pp4, B_prev_pp4;
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reg signed [14:0] R_diff_pp3, G_diff_pp3, B_diff_pp3, R_diff_pp4, G_diff_pp4, B_diff_pp4;
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//H+V syncs + data enable signals®isters
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wire HSYNC_act, VSYNC_act, DE_act;
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reg HSYNC_in_L, VSYNC_in_L;
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reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2, HSYNC_pp3;
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reg VSYNC_1x, VSYNC_2x, VSYNC_3x, VSYNC_4x, VSYNC_5x, VSYNC_pp1, VSYNC_pp2, VSYNC_pp3;
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reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x, DE_pp1, DE_pp2, DE_pp3, DE_3x_prev4x;
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reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2, HSYNC_pp3, HSYNC_pp4, HSYNC_pp5, HSYNC_pp6;
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reg VSYNC_1x, VSYNC_2x, VSYNC_3x, VSYNC_4x, VSYNC_5x, VSYNC_pp1, VSYNC_pp2, VSYNC_pp3, VSYNC_pp4, VSYNC_pp5, VSYNC_pp6;
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reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x, DE_pp1, DE_pp2, DE_pp3, DE_pp4, DE_pp5, DE_pp6, DE_3x_prev4x;
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//registers indicating line/frame change and field type
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reg FID_cur, FID_prev, FID_1x;
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@ -112,16 +115,18 @@ reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_2x_
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reg [2:0] hcnt_2x_opt_ctr, hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
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wire [10:0] vcnt_act;
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reg [10:0] vcnt_tvp, vcnt_1x, vcnt_2x, vcnt_3x, vcnt_4x, vcnt_5x; //max. 2047
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reg [11:0] linebuf_hoffset_pp1;
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reg hoffset_changed_pp1;
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//other counters
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wire [2:0] line_id_act, col_id_act;
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reg [2:0] line_id_pp1, line_id_pp2, col_id_pp1, col_id_pp2;
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reg [2:0] line_id_pp1, line_id_pp2, line_id_pp3, line_id_pp4, line_id_pp5, col_id_pp1, col_id_pp2, col_id_pp3, col_id_pp4, col_id_pp5;
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reg [11:0] hmax[0:1];
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reg line_idx;
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reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
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reg [2:0] line_out_idx_5x;
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reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
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reg mask_enable_pp1, mask_enable_pp2, mask_enable_pp3;
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reg mask_enable_pp1, mask_enable_pp2, mask_enable_pp3, mask_enable_pp4, mask_enable_pp5, mask_enable_pp6;
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//helper registers for sampling at synchronized clock edges
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reg pclk_1x_prev3x;
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@ -152,6 +157,8 @@ reg [2:0] H_OPT_SAMPLE_SEL;
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reg [9:0] H_L5BORDER;
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reg [3:0] X_MASK_BR;
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reg [7:0] X_SCANLINESTR;
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reg [5:0] X_REV_LPF_STR;
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reg X_REV_LPF_ENABLE;
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//clk27 related registers
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reg VSYNC_in_cc_L, VSYNC_in_cc_LL, VSYNC_in_cc_LLL;
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@ -197,6 +204,24 @@ function [7:0] apply_mask;
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end
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endfunction
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function [7:0] apply_reverse_lpf;
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input enable;
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input [7:0] data;
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input [7:0] data_prev;
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input signed [14:0] diff;
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reg signed [12:0] data_prev_x;
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reg signed [10:0] result;
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begin
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data_prev_x = (data_prev << 4);
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result = (data_prev_x - diff) >>> 4;
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if (enable)
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apply_reverse_lpf = (result < 0) ? 8'h00 : (result > 255) ? 8'hFF : result;
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else
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apply_reverse_lpf = data;
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end
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endfunction
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//Mux for active data selection
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//
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@ -368,6 +393,8 @@ begin
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line_id_pp1 <= line_id_act;
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col_id_pp1 <= col_id_act;
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mask_enable_pp1 <= ((hcnt_act < H_AVIDSTART+H_MASK) | (hcnt_act >= H_AVIDSTART+H_ACTIVE-H_MASK) | (vcnt_act < V_AVIDSTART+V_MASK) | (vcnt_act >= V_AVIDSTART+V_ACTIVE-V_MASK));
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linebuf_hoffset_pp1 <= linebuf_hoffset;
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hoffset_changed_pp1 <= (linebuf_hoffset_pp1 != linebuf_hoffset);
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HSYNC_pp2 <= HSYNC_act;
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VSYNC_pp2 <= VSYNC_act;
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@ -375,21 +402,72 @@ begin
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line_id_pp2 <= line_id_pp1;
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col_id_pp2 <= col_id_pp1;
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mask_enable_pp2 <= mask_enable_pp1;
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// Optimized modes repeat pixels. Save previous pixel only when linebuffer offset changes.
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if (hoffset_changed_pp1) begin
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R_prev_pp2 <= R_act;
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G_prev_pp2 <= G_act;
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B_prev_pp2 <= B_act;
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end
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R_pp3 <= apply_scanlines(V_SCANLINEMODE, R_act, X_SCANLINESTR, V_SCANLINEID, line_id_pp2, col_id_pp2, FID_1x);
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G_pp3 <= apply_scanlines(V_SCANLINEMODE, G_act, X_SCANLINESTR, V_SCANLINEID, line_id_pp2, col_id_pp2, FID_1x);
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B_pp3 <= apply_scanlines(V_SCANLINEMODE, B_act, X_SCANLINESTR, V_SCANLINEID, line_id_pp2, col_id_pp2, FID_1x);
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R_pp3 <= R_act;
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G_pp3 <= G_act;
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B_pp3 <= B_act;
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HSYNC_pp3 <= HSYNC_pp2;
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VSYNC_pp3 <= VSYNC_pp2;
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DE_pp3 <= DE_pp2;
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line_id_pp3 <= line_id_pp2;
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col_id_pp3 <= col_id_pp2;
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mask_enable_pp3 <= mask_enable_pp2;
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R_out <= apply_mask(mask_enable_pp3, R_pp3, X_MASK_BR);
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G_out <= apply_mask(mask_enable_pp3, G_pp3, X_MASK_BR);
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B_out <= apply_mask(mask_enable_pp3, B_pp3, X_MASK_BR);
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HSYNC_out <= HSYNC_pp3;
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VSYNC_out <= VSYNC_pp3;
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DE_out <= DE_pp3;
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R_prev_pp3 <= R_prev_pp2;
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G_prev_pp3 <= G_prev_pp2;
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B_prev_pp3 <= B_prev_pp2;
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// Reverse LPF step1
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R_diff_pp3 <= (R_prev_pp2 - R_act);
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G_diff_pp3 <= (G_prev_pp2 - G_act);
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B_diff_pp3 <= (B_prev_pp2 - B_act);
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R_pp4 <= R_pp3;
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G_pp4 <= G_pp3;
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B_pp4 <= B_pp3;
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HSYNC_pp4 <= HSYNC_pp3;
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VSYNC_pp4 <= VSYNC_pp3;
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DE_pp4 <= DE_pp3;
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line_id_pp4 <= line_id_pp3;
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col_id_pp4 <= col_id_pp3;
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mask_enable_pp4 <= mask_enable_pp3;
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R_prev_pp4 <= R_prev_pp3;
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G_prev_pp4 <= G_prev_pp3;
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B_prev_pp4 <= B_prev_pp3;
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// Reverse LPF step2
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R_diff_pp4 <= (R_diff_pp3 * X_REV_LPF_STR);
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G_diff_pp4 <= (G_diff_pp3 * X_REV_LPF_STR);
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B_diff_pp4 <= (B_diff_pp3 * X_REV_LPF_STR);
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R_pp5 <= apply_reverse_lpf(X_REV_LPF_ENABLE, R_pp4, R_prev_pp4, R_diff_pp4);
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G_pp5 <= apply_reverse_lpf(X_REV_LPF_ENABLE, G_pp4, G_prev_pp4, G_diff_pp4);
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B_pp5 <= apply_reverse_lpf(X_REV_LPF_ENABLE, B_pp4, B_prev_pp4, B_diff_pp4);
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HSYNC_pp5 <= HSYNC_pp4;
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VSYNC_pp5 <= VSYNC_pp4;
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DE_pp5 <= DE_pp4;
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line_id_pp5 <= line_id_pp4;
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col_id_pp5 <= col_id_pp4;
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mask_enable_pp5 <= mask_enable_pp4;
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R_pp6 <= apply_scanlines(V_SCANLINEMODE, R_pp5, X_SCANLINESTR, V_SCANLINEID, line_id_pp5, col_id_pp5, FID_1x);
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G_pp6 <= apply_scanlines(V_SCANLINEMODE, G_pp5, X_SCANLINESTR, V_SCANLINEID, line_id_pp5, col_id_pp5, FID_1x);
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B_pp6 <= apply_scanlines(V_SCANLINEMODE, B_pp5, X_SCANLINESTR, V_SCANLINEID, line_id_pp5, col_id_pp5, FID_1x);
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HSYNC_pp6 <= HSYNC_pp5;
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VSYNC_pp6 <= VSYNC_pp5;
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DE_pp6 <= DE_pp5;
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mask_enable_pp6 <= mask_enable_pp5;
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R_out <= apply_mask(mask_enable_pp6, R_pp6, X_MASK_BR);
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G_out <= apply_mask(mask_enable_pp6, G_pp6, X_MASK_BR);
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B_out <= apply_mask(mask_enable_pp6, B_pp6, X_MASK_BR);
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HSYNC_out <= HSYNC_pp6;
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VSYNC_out <= VSYNC_pp6;
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DE_out <= DE_pp6;
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end
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//Generate a warning signal from horizontal instability or PLL sync loss
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@ -559,6 +637,9 @@ begin
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H_OPT_SAMPLE_MULT <= h_info2[12:10];
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H_OPT_STARTOFF <= h_info2[9:0];
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X_REV_LPF_ENABLE <= (extra_info[12:8] != 5'b00000);
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X_REV_LPF_STR <= (extra_info[12:8] + 6'd16);
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X_MASK_BR <= extra_info[7:4];
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X_SCANLINESTR <= ((extra_info[3:0]+8'h01)<<4)-1'b1;
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end
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File diff suppressed because it is too large
Load Diff
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@ -306,7 +306,8 @@ status_t get_status(tvp_input_t input, video_format format)
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(tc.h_mask != cm.cc.h_mask) ||
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(tc.v_mask != cm.cc.v_mask) ||
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(tc.mask_br != cm.cc.mask_br) ||
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(tc.ar_256col != cm.cc.ar_256col))
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(tc.ar_256col != cm.cc.ar_256col) ||
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(tc.reverse_lpf != cm.cc.reverse_lpf))
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status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
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if (tc.sampler_phase != cm.cc.sampler_phase) {
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@ -364,8 +365,8 @@ status_t get_status(tvp_input_t input, video_format format)
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// v_info: [31:29] [28:27] [26] [25:20] [19:17] [16:11] [10:0]
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// | V_MULTMODE[2:0] | V_SCANLINEMODE[1:0] | V_SCANLINEID | V_MASK[5:0] | V_SYNCLEN[2:0] | V_BACKPORCH[5:0] | V_ACTIVE[10:0] |
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//
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// extra: [31:8] [7:4] [3:0]
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// | | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] |
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// extra: [31:13] [12:8] [7:4] [3:0]
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// | | X_REV_LPF_STR | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] |
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//
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void set_videoinfo()
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{
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@ -460,7 +461,8 @@ void set_videoinfo()
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(video_modes[cm.id].v_synclen<<17) |
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(v_backporch<<11) |
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v_active);
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IOWR_ALTERA_AVALON_PIO_DATA(PIO_6_BASE, (cm.cc.mask_br<<4) |
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IOWR_ALTERA_AVALON_PIO_DATA(PIO_6_BASE, (cm.cc.reverse_lpf<<8) |
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(cm.cc.mask_br<<4) |
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cm.cc.sl_str);
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}
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@ -33,6 +33,7 @@
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#define VSYNC_THOLD_MAX 200
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#define SD_SYNC_WIN_MAX 255
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#define PLL_COAST_MAX 5
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#define REVERSE_LPF_MAX 31
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#define SL_MODE_MAX 2
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#define SL_TYPE_MAX 2
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@ -77,6 +78,7 @@ typedef struct {
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alt_u8 post_coast;
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alt_u8 full_tx_setup;
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alt_u8 vga_ilace_fix;
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alt_u8 reverse_lpf;
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#ifdef ENABLE_AUDIO
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alt_u8 audio_dw_sampl;
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alt_u8 audio_swap_lr;
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@ -135,6 +135,7 @@ MENU(menu_postproc, P99_PROTECT({ \
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{ LNG("Horizontal mask","ｽｲﾍｲﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.h_mask, OPT_NOWRAP, 0, HV_MASK_MAX, pixels_disp } } },
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{ LNG("Vertical mask","ｽｲﾁｮｸﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.v_mask, OPT_NOWRAP, 0, HV_MASK_MAX, pixels_disp } } },
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{ LNG("Mask brightness","ﾏｽｸｱｶﾙｻ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.mask_br, OPT_NOWRAP, 0, HV_MASK_MAX_BR, value_disp } } },
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{ "Reverse LPF", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.reverse_lpf, OPT_NOWRAP, 0, REVERSE_LPF_MAX, value_disp } } },
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}))
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MENU(menu_compatibility, P99_PROTECT({ \
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Binary file not shown.
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@ -2,11 +2,11 @@
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<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
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<BspType>hal</BspType>
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<BspVersion>default</BspVersion>
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<BspGeneratedTimeStamp>Aug 8, 2017 11:42:37 PM</BspGeneratedTimeStamp>
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<BspGeneratedUnixTimeStamp>1502224957695</BspGeneratedUnixTimeStamp>
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<BspGeneratedLocation>./</BspGeneratedLocation>
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<BspGeneratedTimeStamp>27-sep-2017 12:31:17</BspGeneratedTimeStamp>
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<BspGeneratedUnixTimeStamp>1506508277524</BspGeneratedUnixTimeStamp>
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<BspGeneratedLocation>D:\ossc\software\sys_controller_bsp</BspGeneratedLocation>
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<BspSettingsFile>settings.bsp</BspSettingsFile>
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<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
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<SopcDesignFile>..\..\sys.sopcinfo</SopcDesignFile>
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<JdiFile>default</JdiFile>
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<Cpu>nios2_qsys_0</Cpu>
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<SchemaVersion>1.9</SchemaVersion>
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
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<!-- Format version 17.0 595 (Future versions may contain additional information.) -->
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<!-- 2017.08.09.23:56:57 -->
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<!-- 2017.09.27.11:57:11 -->
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<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1502312217</value>
|
||||
<value>1506506231</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
|
|
|
|||
Loading…
Reference in New Issue