4 Commits

Author	SHA1	Message	Date
marqs	9feb96888b	fix PLL reference clock switchover logic	2019-10-09 23:58:55 +03:00
marqs	9d496383c3	optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl	2019-10-06 23:54:32 +03:00
marqs	3b19b2843c	Preliminary Line5x implementation	2017-01-29 13:02:12 +02:00
marqs	388c464f63	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00