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9d496383c3
ossc/ip/pll_reconfig
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marqs 9d496383c3 optimize clock network 
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
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inc optimize clock network 2019-10-06 23:54:32 +03:00
pll_reconfig_hw.tcl optimize clock network 2019-10-06 23:54:32 +03:00
pll_reconfig_sw.tcl optimize clock network 2019-10-06 23:54:32 +03:00
pll_reconfig_top.sv optimize clock network 2019-10-06 23:54:32 +03:00