marqs 9d496383c3 optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl		2019-10-06 23:54:32 +03:00
..
altera_epcq_controller_mod	move bitswap inside epcq_controller driver	2018-10-09 23:16:37 +03:00
altera_jtag_avalon_master_mod	free up 1 M9K by modifying altera_jtag_avalon_master	2019-10-03 23:47:59 +03:00
hw_crc32_qsys	replace nios crcCI with hw_crc32 qsys module	2018-10-07 23:38:26 +03:00
i2c_opencores	i2c_opencores: fix compilation warnings	2018-10-07 23:34:29 +03:00
osd_generator	osd_generator: add M9K support to allow larger character array	2019-10-05 11:33:59 +03:00
pll_reconfig	optimize clock network	2019-10-06 23:54:32 +03:00
pulpino_qsys@b11dd7718e	integrate zero-riscy	2018-10-06 13:19:12 +03:00
sc_config	add mask color option	2019-09-30 19:31:05 +03:00