2014-11-10 14:16:45 +00:00
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#ifndef __ACIA_H__
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#define __ACIA_H__
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2014-10-18 11:33:48 +00:00
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struct acia {
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2014-11-10 14:16:45 +00:00
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2018-08-13 13:41:23 +00:00
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// status bits
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2014-11-10 14:16:45 +00:00
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//
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2018-08-13 13:41:23 +00:00
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static const uint8_t rdrf = 1 << 0;
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static const uint8_t tdre = 1 << 1;
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static const uint8_t dcd = 1 << 2;
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static const uint8_t cts = 1 << 3;
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static const uint8_t fe = 1 << 4;
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static const uint8_t ovrn = 1 << 5;
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static const uint8_t pc = 1 << 6;
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static const uint8_t irq = 1 << 7;
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2014-10-18 11:33:48 +00:00
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2014-11-10 14:16:45 +00:00
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// control operations (four combinable groups)
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//
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2018-08-13 13:41:23 +00:00
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static const uint8_t cd1 = 0x00; // divide by 1
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static const uint8_t cd16 = 0x01; // divide by 16
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static const uint8_t cd64 = 0x02; // divide by 64
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static const uint8_t reset = 0x03; // master reset
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2014-10-18 11:33:48 +00:00
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2018-08-13 13:41:23 +00:00
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static const uint8_t ws7e2 = 0 << 2; // parity
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static const uint8_t ws7o2 = 1 << 2;
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static const uint8_t ws7e1 = 2 << 2;
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static const uint8_t ws7o1 = 3 << 2;
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static const uint8_t ws8n2 = 4 << 2;
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static const uint8_t ws8n1 = 5 << 2;
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static const uint8_t ws8e1 = 6 << 2;
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static const uint8_t ws8o1 = 7 << 2;
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2014-10-18 11:33:48 +00:00
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2018-08-13 13:41:23 +00:00
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static const uint8_t lrts_dti = 0 << 5; // /rts, disable trans irq
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static const uint8_t lrts_eti = 1 << 5; // /rts, enable
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static const uint8_t hrts_dti = 2 << 5; // rts, disable
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static const uint8_t lrts_dti_brk = 3 << 5; // /rts, disable, send brk
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2014-10-18 11:33:48 +00:00
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2018-08-13 13:41:23 +00:00
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static const uint8_t eri = 1 << 7; // enable receive interrupt
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2014-10-18 11:33:48 +00:00
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};
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2014-11-10 14:16:45 +00:00
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#endif
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