David Banks
deb6833f8a
Z80: updated segdefs.js based on new boundary tracing algorithm
2018-10-26 16:40:14 +01:00
David Banks
296cd01f84
All: fix zoomToBox to scale selection to fill 80% of the window
2018-10-14 13:34:52 +01:00
David Banks
8e799d6922
All: fix zoomToBox to make use of grChipOffsetX/Y (tested on all chips)
2018-10-14 13:07:25 +01:00
David Banks
a4ed7a9178
Z80: updated transdefs to have accurate bounding box for transistors
2018-10-14 12:28:25 +01:00
David Banks
9795b463ac
Z80: Updated nodenames.js to include warning about manual editing
2018-10-12 13:51:06 +01:00
David Banks
b384fb552f
Z80: Update netlist to fix the IM2 vector issue (missing pass transistor)
2018-10-12 13:08:57 +01:00
David Banks
bf63c33552
All: subtract grChipOffsetX/Y from coordiates given to user so the match the PNGs
2018-10-12 13:08:29 +01:00
David Banks
9760663cc1
Z80: avoid the need to invert the register values in Javascript
2018-10-12 12:40:59 +01:00
David Banks
3ae93282ba
Z80: switch to machine generates nodenames.js (please don't edit\!)
2018-10-12 12:30:03 +01:00
David Banks
ab53a12b2e
Z80: added pla signals to nodenames.js
2018-10-11 12:52:57 +01:00
David Banks
a92f443ac1
Z80: fix stepBack(), drive IntAck value of 0xe9, add lots more internal busses (with Ed)
2018-10-09 22:01:28 +01:00
David Banks
86e6e116d7
All: Fix a hard-coded nodes array length in stateString()
2018-10-09 21:59:27 +01:00
David Banks
f360557572
Z80: override chipsim getNodeValue() to better model charge sharing
2018-10-08 10:33:44 +01:00
David Banks
5005774b1b
Z80: updated handleBusRead() to leave the databus at 0xFF between reads
2018-10-08 10:27:36 +01:00
David Banks
924074e305
Z80: Updated netlist using data that include burried contact at 488,2761 (Ken, 2014)
2018-10-07 13:30:52 +01:00
Ed Spittles
b0c40b9e7b
add URL control of some Z80 inputs
2018-10-06 13:58:37 +01:00
BigEd
74762264c1
Merge pull request #54 from hoglet67/Z80
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Visual Z80: work towards interrupt support
2018-09-30 16:44:22 +01:00
David Banks
6fcb3077eb
Z80: In INTACK cycle, force 0xFF onto the databus
2018-09-30 15:14:40 +01:00
David Banks
cbebb0e11d
Z80: Added additional nodenames for int/nmi
2018-09-30 15:14:40 +01:00
BigEd
2612132999
Merge pull request #53 from TReed0803/master
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[6502] Adding expert wire toggles for SO pin
2018-09-30 14:43:33 +01:00
Trent Reed
8327a36826
Adding expert wire toggles for SO pin
2018-09-29 19:58:25 -07:00
BigEd
886efe1d5a
Merge pull request #52 from hoglet67/Z80
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Work so far on Visual Z80
2018-09-29 18:49:09 +01:00
David Banks
d9c92ebdc3
Z80: corrected typo in flag name
2018-09-22 16:29:19 +01:00
David Banks
651a1753b7
Z80: update test program
2018-09-22 15:27:27 +01:00
David Banks
f5cada53f7
Z80: Updated transdefs.js with a version that replaces trap transistor with a hard short it's drain to ground (just connecting trap gate to VCC was not sufficient)
2018-09-22 14:34:53 +01:00
David Banks
7d579fa4aa
Z80: whitespace only
2018-09-22 11:02:18 +01:00
David Banks
e33f40e60c
Z80: Corrected fetch state machine to cover all cases correctly
2018-09-22 10:58:48 +01:00
David Banks
379d2d1ea1
Z80: Seperate A/F and format flags individually
2018-09-22 09:45:51 +01:00
David Banks
59792d75fc
All: added variables for grChipOffsetX/gfChipOffsetY (previously hardcoded to 400/0)
2018-09-22 09:30:47 +01:00
David Banks
225b49a6d8
Z80: Correct bounding box for transistor in transdefs.js
2018-09-21 22:00:51 +01:00
David Banks
3de51801ea
Z80: Updated test program to include call
2018-09-21 18:04:18 +01:00
David Banks
2f882d7d34
Z80: Start with clock high
2018-09-21 18:03:50 +01:00
David Banks
b9e235fac2
Z80: display remapped registers (so INC D always increments D)
2018-09-21 17:48:51 +01:00
David Banks
0e4c3e0ab0
Z80: Added disassembly
2018-09-21 16:51:58 +01:00
David Banks
767e2492be
Z80: Set grCanvasSize to 5000, so mistakes are clearer
2018-09-21 10:32:20 +01:00
David Banks
95f9d52306
Z80: Adjusted chip/canvas size and max zoom
2018-09-21 10:32:20 +01:00
David Banks
646f22b79e
Z80: segdefs.js now contains polygon information
2018-09-21 10:32:20 +01:00
David Banks
2ff43fafb3
Z80: Expose alterate register state and register set selection flipflops
2018-09-19 18:52:43 +01:00
David Banks
8a9fe6f57e
Extended test program to test simple memory writes
2018-09-19 15:07:27 +01:00
David Banks
3315f309a7
Added EXX to test program, as we seem to start off with alternative BC/DE/HL active
2018-09-19 14:45:41 +01:00
David Banks
85058171b2
Z80: Added ir and wr registers
2018-09-19 13:50:31 +01:00
David Banks
7a0cb72539
Initial checking of chip-z80
2018-09-19 13:27:39 +01:00
Ed Spittles
0a6866f10c
Add two signals to DPControl fixing #50
2018-05-29 10:51:02 +01:00
BigEd
5b15e2d6c9
Merge pull request #48 from mmfoerster/master
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Corrected and expanded the time state readout (the "TState" pseudobus).
2018-05-06 11:24:14 +01:00
BigEd
e6e446a256
Merge pull request #49 from trebonian/BigEd-patch-1
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Updating links, e-tradition is now masswerk
2018-05-06 10:20:26 +01:00
BigEd
bd0356f2a0
Update index.html
2018-05-06 10:20:00 +01:00
BigEd
096f6bbcf8
Updating links, e-tradition is now masswerk
2018-05-06 10:18:22 +01:00
mmfoerster
698312b98e
Corrected and expanded the time state readout (the "TState" pseudobus).
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The occurrences of T6 and T1 have been corrected. T6 now only occurs when a BRK
instruction is executing, it is a synonym for when the VEC1 node is logic high.
T1 now occurs when node 862 is logic high, which drives the SYNC pin, among
other control effects.
Formerly, T1 and T6 were displayed only when all the nodes that affect the PLA
were inactive. Node 1357's state was used in that case to choose between
displaying T1 (1357 high) or T6 (1357 low). That turned out to be incorrect
pair of inferences. The result was that T1 was absent when it should have been
present (when T+ was present without T0), and T6 was present when it should
have been absent (for instructions other than BRK). Among the corrective
changes, node 1357 is no longer consulted.
Expansion of state display adds V0, SD1, and SD2 indications. The last two are
in their own field (an eighth field). V0 is in the seventh field (square
bracketed, the same field occupied by T1 and T6). It is a two-character
representation of node VEC0 being at logic high. VEC0 high causes VEC1 to be
high one cycle later, which is T6. V0 is, like T6, activated only by execution
of a BRK instruction.
SD1 and SD2 are nodes 440 and 1258 respectively, which lie in the RCL block
outside of the timing generation (clock) block. They serve the needs of the
RMW (Read-Modify-Write) instructions for their addressing modes that use
external memory instead of the accumulator.
All of the corrected and new features has increased the total number of
displayed states to 24 from 10. Hopefully, this is the ultimate, final,
most fully comprehensive clock display possible, but we'll see.
2017-12-15 13:47:24 -05:00
BigEd
bd45334147
Merge pull request #47 from mmfoerster/master
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Added 6502 time code display as "TState" pseudo-bus - see wiki
2017-10-30 18:35:22 +00:00
mmfoerster
7efe4fb8c7
Added comments to allTCStates() referring to the 6502_Timing_States wiki page.
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The state labeling is not completely correct or complete regarding T5 and T6
(especially the latter). More investment will be forthcoming.
2017-10-30 14:08:57 -04:00
