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@ -7,7 +7,7 @@ module ACI (
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input clk, // clock signal
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input clk, // clock signal
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input cpu_clken, // CPU clock enable
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input cpu_clken, // CPU clock enable
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input [15:0] address, // address bus
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input [15:0] addr, // address bus
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output reg [7:0] dout, // 8-bit data bus (output)
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output reg [7:0] dout, // 8-bit data bus (output)
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output reg tape_out, // tape output
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output reg tape_out, // tape output
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@ -19,16 +19,16 @@ module ACI (
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initial
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initial
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$readmemh("roms/aci.hex", rom_data, 0, 255);
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$readmemh("roms/aci.hex", rom_data, 0, 255);
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wire io_range = address >= 16'hC000 && address <= 16'hC0FF;
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wire io_range = addr >= 16'hC000 && addr <= 16'hC0FF;
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wire [7:0] read_address = io_range ? { address[7:1], address[0] & tape_in } : address[7:0];
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wire [7:0] read_addr = io_range ? { addr[7:1], addr[0] & tape_in } : addr[7:0];
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(cpu_clken & io_range)
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if(cpu_clken & io_range)
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tape_out <= ~tape_out;
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tape_out <= ~tape_out;
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dout <= rom_data[read_address];
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dout <= rom_data[read_addr];
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end
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end
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endmodule
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endmodule
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@ -224,7 +224,7 @@ wire CASOUT;
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ACI ACI(
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ACI ACI(
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.clk(sys_clock),
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.clk(sys_clock),
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.cpu_clken(cpu_clken),
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.cpu_clken(cpu_clken),
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.address(sdram_addr[15:0]),
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.addr(sdram_addr[15:0]),
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.dout(aci_dout),
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.dout(aci_dout),
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.tape_in(CASIN),
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.tape_in(CASIN),
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.tape_out(CASOUT),
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.tape_out(CASOUT),
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