Unknown
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aa70ce407a
|
Updated RAM board BOM
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2019-02-16 22:25:30 +01:00 |
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Unknown
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bcedf3cb12
|
Fixed RAM board block select logic
|
2019-02-16 22:24:28 +01:00 |
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Unknown
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8ad4584e91
|
Added RAM README
|
2019-01-14 22:25:28 +01:00 |
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Unknown
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d0f6b369fd
|
Changed VDU CS logic ins schematic
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2018-12-29 13:56:20 +01:00 |
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Unknown
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f36f8700e3
|
Flipped decoder inputs, added details to silkscreen.
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2018-12-23 01:12:14 +01:00 |
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Unknown
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6fd7df5eb0
|
Enhanced RAM/ROM board, routing done
|
2018-12-22 17:09:04 +01:00 |
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Unknown
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7dbb3f715b
|
Schematic done for enhanced RAM/ROM board
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2018-12-21 19:00:00 +01:00 |
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Unknown
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e51a21e59a
|
RAM revision B
Fixed silkscreen notes by swapping high/low text, moved around tracks to make it a little more compact.
|
2017-06-10 17:50:00 +02:00 |
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Unknown
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12f925f831
|
Added pictures of working setup
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2017-06-02 20:24:48 +02:00 |
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Unknown
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814df351cb
|
Renamed some pins
|
2017-06-01 19:41:30 +02:00 |
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Unknown
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789a7bdd18
|
Exported all schematics to PDF
|
2017-05-31 01:10:27 +02:00 |
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Unknown
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5bcb7ba543
|
Exported files
|
2017-05-15 22:54:58 +02:00 |
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Unknown
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4197312ab0
|
Updated net lists
|
2017-05-14 21:51:11 +02:00 |
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Unknown
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ef9b1b5ff8
|
Added files
|
2017-05-14 21:08:06 +02:00 |